The impedance matching of the CLK waveform is not good for my SPI communication signal, and it seems to be a count error of the data signal.
Question (1): Does the ADS131M06 SPI input port have features like schmit trriger?
Question (2): Without the schmit function, how do I know the actual threshold voltage of a device?
Thank you for sharing of your ideas.
Hello,
Yes, the SPI inputs on the ADS131M06 are Schmitt triggers. So they latch to the state as defined by the threshold below and then need to exceed the opposite threshold.
In general, your situation looks very strange. The text in the datasheet is clear that DOUT is not supposed to transition on SCLK falling edges. As a result, there's two possibilities going through my mind.
The first is exploratory. I'd be interested to see /CS and /DRDY on the same plot as they might give clues to what might be happening. In addition, it looks like you sent the equivalent of a NULL. I have no confirmation from this picture that SCLK toggled the necessary amount of times to complete a SPI frame. If the SPI frame is short cycled, it will flag an error in the response of the NULL command. When implementing SPI, you cannot just check to see if some arbitrary amount of SCLKs give some data. The entire frame needs to be completed or behavior (and ADC data) will be unpredicatble.
The second is that signal degradation is an issue here. If the rise and fall time contributes more than, as a rule of thumb, 1-5% of the total clock period, then the signals are running too fast for the SPI bus. This could be caused by poor layout, or long wires connecting between MCU and ADC, or other. I would slow the entire SPI transaction down until rise time and fall time are "negligible" and see if the issue goes away.
Best,
-Cole
