• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 47 subscribers
  • Views 201 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AMC3306M25: Questions about DCDC_OUT voltage getting lower than 3.5V.

Kazuya Nakai59
Guru 20530 points
Part Number: AMC3306M25

Hello guys,

One of my customers is evaluating AMC3306M25 on their own board. their board has one AMC3306 and they assembled 30 sheets of the board.
They observed DCDC_OUT terminal voltage of  AMC3306M25 high side on each board. In the result, they found DCDC_OUT voltage on 3 or 4 sheet were about 1.86V not typical voltage(3.5V). Also HLDO_OUT voltage was almost zero when DCDC_OUT is 1.86V.
One of 2 channel opamp IC, one of 1 channel opamp IC, two of 0.1uF bypass capacitor and total 40kohm voltage divider are connected to the HLDO_OUT.

This DCDC_OUT voltage drop phenomenon is happened sometimes. And the phenomenon is disappeared when the power of VDD is turned off and on again.

First question are the below.

Q1. Do you know a phenomenon like this and do you know what the cause is? Is there any countermeasure?

I have another question.

Q2. The device datasheet shows device startup timing at Figure 6-2 on page 10.
       I think CLKIN signal should be started to input after VDD powered up. 
      Is there any timing limitation between VDD power up timing and CLKIN signal start timing?
      For example, is it OK to start CLKIN signal input after 100ms elapsed from VDD powered up?

Your reply would be much appreciated.

Best regards,

Kazuya.

  • 0
    TI__Mastermind 22950 points

    Hi Kazuya,

    Q1. I haven't personally come across this issue before. Can you provide additional details like a schematic and some oscilloscope captures of the DCDC voltage and HLDO_OUT? Are you by chance loading HLDO_OUT? I should note that HLDO_OUT can only source 1mA so if you are loading and trying to pull > 1mA there may be some issues here. 

    Q2. You are correct in that VDD should be powered on first. Reason being is that there is an absolute digital input of VDD + 0.3V so if VDD is not powered and you are providing CLKIN, you will violate this specification. 

    Regards,
    Aaron Estrada

  • 0 in reply to Aaron Estrada
    Guru 20530 points

    Hi Aaron

    Thank you very much for your reply.

    Could I ask you a few additional questions as the below?

    Q1. About VDD power on and CLKIN signal input timing.
          Is it OK to start CLKIN signal input after 100ms elapsed from VDD powered up?

    Q2. Can HLDO_OUT voltage recovered to 3.2V(Typ) when heavy load (>1mA) is released after heavy loading (HLDO_OUT load is over 1mA)?  

    The customer is taking some waveforms. But they don't want disclose the waveforms on this thread.

    So could you please tell me your e-mail address or could I send you friend ship request to share their waveforms?

    Thank you again and best regards,

    Kazuya.

  • 0 in reply to Kazuya Nakai59
    TI__Mastermind 22950 points

    Hi Kazuya-san,

    Update for E2E:

    The dip in DCDC_OUT was due to providing a clock greater than the specified clock frequency range in the data sheet. 

    I will close this thread since we have taken this offline. 

    Regards,
    Aaron Estrada

  • 0 in reply to Aaron Estrada
    Guru 20530 points

    Hi Aaron,

    Thank you very much for your strong supports.

    The cause was higher clock frequency than 21MHz, the maximum frequency spec of CLKIN.

    Thank you again and best regards,

    Kazuya.