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ADC3683EVM: Wrong DCLKIN calculation in Eval Brd Software?

Part Number: ADC3683EVM
Other Parts Discussed in Thread: ADC3683,

For our application we would like to use the ADC3683 in 0p5 wire mode. I tried to set the software for the EvalBrd accordingly using real decimation with a decimation factor of 4 according to table 8-5 from the datasheet on page 36. The calalculated DCLKIN frequency for a sampling rate of 65 MSPS was 73.125 MHz instead of the 292.5 MHz stated in the datasheet.

Please advise on how to set the software to the parameters from the datasheet.

Furthermore I noticed that only 2 wire mode is supported by the onboard clock generator IC. Is there any possibility to use the clock generator IC of the EvalBrd for 0p5 wire mode as well e.g. by replacing the quarz oscillator or feeding an external clock signal into the secref input? If so, how do I tell the software to set the clock generator IC correctly with the changed quarz or by using the secref input?

Thank you in advance!

  • Hi Lukas,

    I am checking on this and will get back to you soon.

    Regards, Amy

  • Hi Lukas,

    I apologize for the delay, I am still checking into this and will get back to you in the next few days.

    Regards, Amy

  • Hi Amy,

    thank you for looking into this.

    Another thing that I noticed in the log window:

    In the datasheet on page 38, Table 8-7 the configuration steps for changing the interface or decimation factor are listed. 0x13 should be set to 0x01 and then back to 0x00 to load the bit mapping. 

    According to the data written to the ADC over SPI listed in the log window, register 0x13 is never written to. Why is that so?

    Furthermore, register 0x10E is read at the end of the init sequence, but this register is not described in the datasheet. What does it do?

    Best regards and thanks in advance,
    Lukas

  • Hello Lukas,

    You are correct, there is an error in the GUI calculator for the DCLKIN calculation. If you intend to use 18b mode with decimation by 4, the DCLKIN frequency should be 292.5M (as describe in Table 8-5) for ½w mode.

    Chase and I have tested a working solution for you using a python script that configures the clocking chip to the corresponding frequencies for the mode above. I can send this along if this is an acceptable solution for you.

    Thank you again for your patience.

    Regards, Amy

  • Additionally, I set up the ADC3683EVM in the lab and register 0x13 is set to 0x01 and then back to 0x00, as the datasheet describes. This can be seen in the GUI feedback log. Register 0x10E is a engineering development register. It is not recommended to modify this register. 

  • Hello Amy,

    yes, please send me the python program.

    Best regards,

    Lukas

  • Lukas,

    Please see the other thread. I will be closing this thread now.

    Regards, Chase