ADC12DJ3200: foreground calibration

rui gao

Prodigy 20 points

Part Number: ADC12DJ3200
Other Parts Discussed in Thread: LMK04828, LMX2594

嗨，团队，

我使用自己的设计板，FPGA是420T，FPGA的参考时钟和参考时钟由LMK04828产生，LMK连接LMX2594输出ADC器件时钟和参考时钟。示波器可以观察产生的时钟信号。

JMODE1，ILA观察到的同步信号被拉低，但xillnx IP核tdata没有数据输入（K28.5），并且ADC上的前景校准无法完成，0x6A总是读取0C。

这是 ILA 捕获的信号

此致敬意

over 1 year ago

0 rui gao over 1 year ago

Prodigy 20 points

This is register configuration：

assign cfg_mem[ 0] = { 15'h0000,8'hB0 };//reset
assign cfg_mem[ 1] = { 15'h0030,8'hFF };
assign cfg_mem[ 2] = { 15'h0031,8'hFF };
assign cfg_mem[ 3] = { 15'h0032,8'hFF };
assign cfg_mem[ 4] = { 15'h0033,8'hFF };
assign cfg_mem[ 5] = { 15'h0048,8'h03 };// Set serializer pre-emphasis to 3 预加釿
assign cfg_mem[ 6] = { 15'h0200,8'h00 };//Program JESD_EN=0 to stop the JESD204B state machine and allow setting changes.
assign cfg_mem[ 7] = { 15'h0061,8'h00 };//Program CAL_EN=0 to stop the calibration state machine and allow setting changes
assign cfg_mem[ 8] = { 15'h0201,8'h01 };//Program desired JMODE. JMODE=1
assign cfg_mem[ 9] = { 15'h0202,8'h1F };//Program desired KM1 value. KM1 = K-1
assign cfg_mem[ 10] = { 15'h0204,8'h06 };//Program SYNC_SEL as needed.
assign cfg_mem[ 11] = { 15'h003B,8'h03 };//TMSTP input enable and LVPECL
assign cfg_mem[ 12] = { 15'h0205,8'h04 };// testmode 0x00刿0xFF 测试链路屿 RAMP TEST Mode
assign cfg_mem[ 13] = { 15'h0213,8'h07 };// Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples 8*2^7 = 1024 超量稿
assign cfg_mem[ 14] = { 15'h0029,8'h70 };
assign cfg_mem[ 15] = { 15'h0029,8'h73 };
assign cfg_mem[ 16] = { 15'h0061,8'h01 };//Program CAL_EN=1 to enable the calibration state machine.
assign cfg_mem[ 17] = { 15'h0200,8'h01 };// Program JESD_EN=1 to re-start the JESD204B state machine and allow the link to re-start
assign cfg_mem[ 14] = { 15'h006C,8'h00 };//Set CAL_SOFT_TRIG low to reset calibration state machine
assign cfg_mem[ 15] = { 15'h006C,8'h01 };//Set CAL_SOFT_TRIG high to enable calibration
assign cfg_mem[ 18] = { 15'h02C0,8'h00 };
assign cfg_mem[ 19] = { 15'h02C2,8'h00 };
assign cfg_mem[ 20] = { 15'h02C1,8'h1F };