ADC12DJ3200: foreground calibration

This is register configuration：

assign cfg_mem[ 0] = { 15'h0000,8'hB0 };//reset
assign cfg_mem[ 1] = { 15'h0030,8'hFF };
assign cfg_mem[ 2] = { 15'h0031,8'hFF };
assign cfg_mem[ 3] = { 15'h0032,8'hFF };
assign cfg_mem[ 4] = { 15'h0033,8'hFF };
assign cfg_mem[ 5] = { 15'h0048,8'h03 };// Set serializer pre-emphasis to 3 预加釿
assign cfg_mem[ 6] = { 15'h0200,8'h00 };//Program JESD_EN=0 to stop the JESD204B state machine and allow setting changes.
assign cfg_mem[ 7] = { 15'h0061,8'h00 };//Program CAL_EN=0 to stop the calibration state machine and allow setting changes
assign cfg_mem[ 8] = { 15'h0201,8'h01 };//Program desired JMODE. JMODE=1
assign cfg_mem[ 9] = { 15'h0202,8'h1F };//Program desired KM1 value. KM1 = K-1
assign cfg_mem[ 10] = { 15'h0204,8'h06 };//Program SYNC_SEL as needed. 
assign cfg_mem[ 11] = { 15'h003B,8'h03 };//TMSTP input enable and LVPECL
assign cfg_mem[ 12] = { 15'h0205,8'h04 };// testmode 0x00刿0xFF 测试链路屿 RAMP TEST Mode
assign cfg_mem[ 13] = { 15'h0213,8'h07 };// Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples 8*2^7 = 1024 超量稿
assign cfg_mem[ 14] = { 15'h0029,8'h70 };
assign cfg_mem[ 15] = { 15'h0029,8'h73 };
assign cfg_mem[ 16] = { 15'h0061,8'h01 };//Program CAL_EN=1 to enable the calibration state machine.
assign cfg_mem[ 17] = { 15'h0200,8'h01 };// Program JESD_EN=1 to re-start the JESD204B state machine and allow the link to re-start
assign cfg_mem[ 14] = { 15'h006C,8'h00 };//Set CAL_SOFT_TRIG low to reset calibration state machine
assign cfg_mem[ 15] = { 15'h006C,8'h01 };//Set CAL_SOFT_TRIG high to enable calibration
assign cfg_mem[ 18] = { 15'h02C0,8'h00 };
assign cfg_mem[ 19] = { 15'h02C2,8'h00 };
assign cfg_mem[ 20] = { 15'h02C1,8'h1F };

Could you make any troubleshooting suggestions?

I am sorry. It's translated automatically,  I will delate the last question.

Hi Rui,

First, lets make sure FG CAL is running properly. Usually when FG fails calibration, that means that the device is not receiving the CLK. After power-up and before reset please make sure that the device CLK is applied. Can you measure at the input pins of CLK to confirm?

After reset please wait until Register 0x270  bit 0 is high. This bit returns 1 when initialization logic has finished (~250ms) but for debug purposes i'd recommend  1 second wait time and optimize later once you have a working system with your time reference.

assign cfg_mem[ 0] = { 15'h0000,8'hB0 };//reset

wait until init bit is done after reset. register 0x270 bit 0

assign cfg_mem[ 6] = { 15'h0200,8'h00 };//Program JESD_EN=0 to stop the JESD204B state machine and allow setting changes.
assign cfg_mem[ 7] = { 15'h0061,8'h00 };//Program CAL_EN=0 to stop the calibration state machine and allow setting changes

assign cfg_mem[ 1] = { 15'h0030,8'hFF };
assign cfg_mem[ 2] = { 15'h0031,8'hFF };
assign cfg_mem[ 3] = { 15'h0032,8'hFF };
assign cfg_mem[ 4] = { 15'h0033,8'hFF };
assign cfg_mem[ 5] = { 15'h0048,8'h03 };// Set serializer pre-emphasis to 3 预加釿

assign cfg_mem[ 8] = { 15'h0201,8'h01 };//Program desired JMODE. JMODE=1
assign cfg_mem[ 9] = { 15'h0202,8'h1F };//Program desired KM1 value. KM1 = K-1
assign cfg_mem[ 10] = { 15'h0204,8'h06 };//Program SYNC_SEL as needed. 
assign cfg_mem[ 11] = { 15'h003B,8'h03 };//TMSTP input enable and LVPECL
assign cfg_mem[ 12] = { 15'h0205,8'h04 };// testmode 0x00刿0xFF 测试链路屿 RAMP TEST Mode
assign cfg_mem[ 13] = { 15'h0213,8'h07 };// Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples 8*2^7 = 1024 超量稿
assign cfg_mem[ 14] = { 15'h0029,8'h70 };
assign cfg_mem[ 15] = { 15'h0029,8'h73 };
assign cfg_mem[ 16] = { 15'h0061,8'h01 };//Program CAL_EN=1 to enable the calibration state machine.
assign cfg_mem[ 17] = { 15'h0200,8'h01 };// Program JESD_EN=1 to re-start the JESD204B state machine and allow the link to re-start
assign cfg_mem[ 14] = { 15'h006C,8'h00 };//Set CAL_SOFT_TRIG low to reset calibration state machine
assign cfg_mem[ 15] = { 15'h006C,8'h01 };//Set CAL_SOFT_TRIG high to enable calibration
assign cfg_mem[ 18] = { 15'h02C0,8'h00 };
assign cfg_mem[ 19] = { 15'h02C2,8'h00 };
assign cfg_mem[ 20] = { 15'h02C1,8'h1F };

pull from cal_status to FG_DONE

1.This is the device CLK which is at the input pins of CLK is provided by LMX2594:

there seems to be no problem in the signal.

The TI website have a maintenance soon. How can I contact you during maintenance？Please leave a contact detail for me .thank you for your help.

HI Rui,

Just to make sure, your probing the clock as close as possible to the ADC and not at the output of the LMX.

Is the ADC CLK AC coupled from the LMX device?

Also, can you measure the VCM of the clock pins. should match datasheet below.

 I am probing the clock in the ADC AC-coupling capacitor,there seems to be no problem in the signal.

and the VCM of the clock pin within 0.1V.

On my end when i turn off the clock or reduce the clock to certain point then only the init bit will not clear after reset and if no clock FG cal will not finish. Are you using the new produce that i provided?

For the picture that you provided for clock is that just 1 leg(the + CH only) or differential? VCM is on the low side... Can you measure the supply voltages closest to the pin(try the decoupling caps) to make sure they are within datasheet and the source has the proper current rating to supply for the ADC. Can you check the AC caps to clock. Can you share schematic for design?

after powerup and once clk is alive and  reset has been asserted. try following register writes...

0x0200 0x00 // Clear JESD_EN (always before CAL_EN)
0x0061 0x00 // Clear CAL_EN (always after JESD_EN)
0x0201 0x00 // Set JMODE0
0x0202 0x03 // Set KM1=3 so K=4
0x0204 0x01 // Use SYNCSE input, offset binary data, scrambler enabled
0x0213 0x07 // Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples
0x0048 0x03 // Set serializer pre-emphasis to 3
0x0061 0x01 // Set CAL_EN (always before JESD_EN)
0x0200 0x01 // Set JESD_EN (always after CAL_EN)
0x006C 0x00 // Set CAL_SOFT_TRIG low to reset calibration state machine
0x006C 0x01 // Set CAL_SOFT_TRIG high to enable calibration

read register 0x208(JESD_STATUS) and check if PLL_LOCKED is high(bit 2). 

It is differential signal,and I measure the voltages in this place.and this is schematic for ADC clk.

Did you try the sequence i gave you a week ago and measured the supply voltages close the the device?

i'm reattaching it.

after powerup and once clk is alive and  reset has been asserted. try following register writes...

0x0200 0x00 // Clear JESD_EN (always before CAL_EN)
0x0061 0x00 // Clear CAL_EN (always after JESD_EN)
0x0201 0x00 // Set JMODE0
0x0202 0x03 // Set KM1=3 so K=4
0x0204 0x01 // Use SYNCSE input, offset binary data, scrambler enabled
0x0213 0x07 // Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples
0x0048 0x03 // Set serializer pre-emphasis to 3
0x0061 0x01 // Set CAL_EN (always before JESD_EN)
0x0200 0x01 // Set JESD_EN (always after CAL_EN)
0x006C 0x00 // Set CAL_SOFT_TRIG low to reset calibration state machine
0x006C 0x01 // Set CAL_SOFT_TRIG high to enable calibration

read register 0x208(JESD_STATUS) and check if PLL_LOCKED is high(bit 2).