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ADC12DJ3200: some issues

Amy Luo
Expert 6895 points
Part Number: ADC12DJ3200
Other Parts Discussed in Thread: TSW14J57EVM,

Hi team，

One of our customer's issues, I'm forwarding it below, could you please provide some troubleshooting suggestions

When this customer is debugging the ADC12DJ3200 chip in JMODE0, 6GSPS, lane rate = 12Gbps mode, the following will occur:

1. In the ramp test mode, the rx_sync signal output of JESD204B core will drop for a short period of time; normal mode will not  drop rx_sync signal when picking up or collecting continuous wave signals.

2. JESD204B will not relink when rx_sync signal is pulled low for a short period of time.

3. The rx_frame_error signal indicates a byte error when the rx_sync signal is pulled low when the relevant signal is grabbed.

4. Change JMODE0 to JMODE1 with the same sample rate, which is equivalent to reducing the line rate to 6Gbps, and above phenomena does not happen.

Where the problem may be causing the above phenomenon? Is there a problem with the GTX physical link?

Best Regards,

Amy Luo

  • 0
    TI__Mastermind 20541 points

    Hi Amy,

    Based on what is shown above the issue might be caused by signal integrity. To prove this you also try to change the clock frequency for JMODE0 to half the rate which will reduce the serdes rate to 6Gbps and see if the error on JMODE0 goes away. 

    Also you can play with SERDES pre-emphasis settings by changing the register address 0x048 to different values. With ADC12DJ3200EVM and TSW14J57EVM we use the value of 0x3 for pre-emphasis settings. 

    Regards,

    Neeraj