Other Parts Discussed in Thread: TSW14J57EVM,
Hi team,
One of our customer's issues, I'm forwarding it below, could you please provide some troubleshooting suggestions
When this customer is debugging the ADC12DJ3200 chip in JMODE0, 6GSPS, lane rate = 12Gbps mode, the following will occur:
1. In the ramp test mode, the rx_sync signal output of JESD204B core will drop for a short period of time; normal mode will not drop rx_sync signal when picking up or collecting continuous wave signals.
2. JESD204B will not relink when rx_sync signal is pulled low for a short period of time.
3. The rx_frame_error signal indicates a byte error when the rx_sync signal is pulled low when the relevant signal is grabbed.
4. Change JMODE0 to JMODE1 with the same sample rate, which is equivalent to reducing the line rate to 6Gbps, and above phenomena does not happen.
Where the problem may be causing the above phenomenon? Is there a problem with the GTX physical link?
Best Regards,
Amy Luo