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ADC12DJ3200: Line Rate Question

Nicholas Strong
Prodigy 90 points
Part Number: ADC12DJ3200

Can you please confirm the clock rate settings for 6 Gsps sampling rate for the ADC?

My understanding is that in single channel mode, the F_s * 2, so the device clock would need to be at 3 GHz. Is this correct?

Would a 300 MHz JESD clock at 8 channels and a 18.75 MHz SYSREF clock be correct for this sample rate?

  • +1
    TI__Mastermind 20541 points

    Hi Nicholas,

    When using single channel  mode on ADC12DJ3200, sampling frequency = 2x DEVCLOCK For example in JMODE0(Single Channel Mode) 3GHz clock will result in sampling frequency of 6Gsps. 

    Serdes lane rate = DEVCLK X R factor( from the datasheet Table 18. ADC12DJ3200 operating modes)

    For JMODE0 R factor = 4 

    Serdes lane rate = 3GHz X 4 = 12Gbps

    JESD ref clock = SERDES Rate/40 => 12Gbps/40 = 300MHz

    Sysref Frequency = SERDES LANE RATE/(10 x F x K): K = 4 can also be selected from table 18

    =>12Gbps/(10 x 8 x 4) => 37.5MHz or any integer divider of 37.5MHz is valid sysref frequency. 

    If different K value is picked the SYREF frequency will be different for example if K = 32, 

    12Gbps/(10 x 8 x 32) => 4.6875MHz or integer divider of 4.6875MHz should work for sysref frequency. 

    Regards,

    Neeraj