AMC1210: More or less sporadic modulator failure when using the same Modulator and System Clock Frequency at certain voltage levels

Hi Sebastian,

The system clock and the modulator clocks should be able to be run asynchronously. What modulator mode are you using? Modulator mode 3 should use a divided down system clock that is fed into the modulator clock pins. 

Regards,
Aaron Estrada

Can you also let us know which modulator you are using?  

Hello,

• We are using the AMC1035. 
  
  
• We use modulator mode 0

Additionally, it is worth to mention that we don't see invalid conversion results even when this modulator failure occurs.
The results are very precise and undisturbed.

Kind regards

Sebastian 

It may also be worth mentioning that the 20MHz System Clock and the 20MHz Modulator Clock are generated by two seperate quarz generators.
They may experience phase shifting and/or slight differences in their frequencies.

So the system clock may have something like 19.99MHz and the Modulator Clock 20.01MHz. 

May this lead to an issue? (E.g. must the system clock be exactly in phase with the modulator clock or must the system clock be >= the modulator clock at all times? May beat (german: Schwebung) occur? 

Kind regards

Sebastian 

Hi Sebastian,

Interesting detail!  Yes, that could be your issue.  Can you try setting CLKx to be SYS clock in the AMC1210_20_20 setup and disable the second oscillator?  See Table 7 on page 16 as well as the Control Parameter Register description on page 29.

Hello Tom,

sorry, I unfortunately didn't quite get your proposal.

=> Are you talking about a SW configuration? Perhaps you could explain a bit more in detail then on how to realize your proposal on SW side?
=> If you are talking also about HW Change: Unfortunately, we can not use the CLKx signals as outputs and feed the modulator that easy. 

For us, it may be very beneficial to understand exactly, how the modulator clock is observed and how the modulator failure is being generated. 

=> Because the conversion results don't seem to be effected in the slightest, we ask ourself, whether the "Observation" is having an issue and the "modulator clock signal" is not at all faulty.

We of course already measured the modulator clock singal on the AMC1210 and it seems to be perfectly fine. 

Kind regards

Sebastian 

Hi Sebastian,

The 'modulator failure' only looks at the CLKx input, it is not looking at the bitstream or trying to verify the output of the filter itself.  This is noted in Table 4.  I was hoping this would be a small SW change by using SYSCLK as CLKx and feeding that to the modulator.

Hello Tom,

thank you for your answers so far.

May you tell me, how exacty the "modulator failure" looks at the CLKx Input? Like how is the frequency determined? 
Kind regards

Sebastian 

Hi Sebastian,

Yes - give me a day or so and I will provide details on how the Modulator Fault functions.