ADC12DJ3200: Abnormal sampled voltage

our own design

Hi Yin,

Can you please send the front end schematic for the ADC? We can look at it and see what is causing the loss in voltage. 

Regards,

Neeraj

Hi, This is the schematic diagram of ADC12DJ3200.

When ADC12DJ3200 is not welded, we measure the voltage value of VIN1_P as 50mV, that is, the external input VIN1_P-VIN1_N = 100mV.

Hi Dongqiang,

Neeraj is requesting the frontend schematic that goes to the analog input pins. This will help us debug the issue. See attached.

Regards,

Rob

Hi Yin,

I noticed after you change the full scale on your ADC by writing 0x30, 0x31 and 0x32,0x33. You will have calibrate the ADC. by writing 0x006C00 then 0x006C01. 

Also what is you output format data format from the ADC 2's compliment or offset binary. 

Please also send the front end schematic.

Regards,

Neeraj

Hi Neeraj

1.   I tried to write 0x006C00 and 0x006C01，it does not work.

2.  ADC's out format is offset binary.（0x020400）

3. The front end schematic is as follows:

When ADC12DJ3200 is not welded, we use an oscilloscope to measure that the output of the P terminal of LMH6401 is 85mV, and infer that the LVDS output of LMH6401 is 170mV. At this time, the impedance of the oscilloscope is 1M ohm.

When welding the ADC12DJ3200, we used an oscilloscope to measure that the output of the P terminal of LMH6401 is about 40mV, and inferred that the LVDS output of LMH6401 is 80mV. We think the reason for this is that the analog input INA and INB of the ADC12DJ3200 have a 50 ohm pull-down resistance.

When welding the ADC12DJ3200, should the sampling output voltage of the ADC12DJ3200 be 170mV or 80mV?