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ADS131M06: Input referred noise on the low frequency side, such as 5Hz, when using the internal digital filter of the ADS131M06

YOSHIHIKO KURUI
Prodigy 60 points
Part Number: ADS131M06
Other Parts Discussed in Thread: ADS124S08, ADS1248

The ADS131M06 has multiple ADCs and thus consumes more power than the ADS1248 and ADS124S08 ICs that use multiplexers, but the advantage is that it can acquire inter-channel data outputs simultaneously, which allows a shorter time to acquire synchronized data across all channels. We are interested in adopting this IC.

I would like to know if the noise level is the same or better than the above ICs when set in the same bandwidth.

What is the input referred noise value on the low frequency side when using the internal digital filter of the ADS131M06?
The datasheet "Table 7-1. Noise at TA = 25° (μVRMS)" only gives data up to 250 Hz. please tell me the noise at ODR = 1 Hz / 5 Hz / 10 Hz. The gains used are around 32 / 64 /128.

ADS131M06 noise ADC ADS1248 ADS124S08 syncronized data

  • 0
    Prodigy 60 points

    最後の１文はタイプミスのため無視してください。

  • 0
    Prodigy 60 points

    Please disregard the last sentence as it is a typo.

  • 0 in reply to YOSHIHIKO KURUI
    TI__Mastermind 37955 points

    Hi YOSHIHIKO,

    Thank you for considering TI Delta-Sigma ADCs.

    The OSR determines the amount of averaging of the modulator output in the digital filter and so it determines the filter's bandwidth which affects ADC's noise performance. 16384 is the highest OSR which can be configured on ADS131M06, so the table 7-1 in the datasheet has showed the lowest noise from the ADC. One solution you can reduce noise further is averaging the code in your software on your processor.

    The modulator frequency (fMOD) on ADS131M06 is half of the master clock(fCLKIN), so 250SPS data rate can be calculated from the following equation when the fCLKIN is 8.192MHz and the OSR is 16384:       

                                                                      fdatarate = fCLKIN / (2*16384) = 8.192MHz/(2*16384) =250Hz. 

    The minimum clock frequency for any mode (high-resolution, low-power, very low-power) on ADS131M06 is 0.3Mhz, so the lowest data rate is

                                                                      fdatarate_low = fCLKIN / (2*16384) = 0.3MHz/(2*16384) =9.155Hz. 

     You can achieve 10SPS data rate on this ADC if you are able to generate a master clock to meet the requirement.

    When comparing the noise performance between ADS131M06 and ADS124S08, ADS124S08 has lower noise because it can be configured as a lower bandwidth filter in Sinc3 or low-latency filter mode.

    Thanks&regards,

    Dale