ADS1292: ADS1292 Power-Down Current.

Hi,

Did you hold the /PWDN/RESET low long enough - "If PWDN/RESET is held low for longer than 2^9 fMOD clock cycles, the device is powered down."

"if 2^10 clock elapses it is powered down."

May I ask how did you measure the current to VDD(AVDD, DVDD) during the power down?

Also, Does the source of the VDD supply to ADS only, not to any other device(s), OpAmp, or resistor(s)?

Thanks

1. The PCB has only ADS1292 and its passive

2. AVDD and DVDD are shorted. We are connecting supply to VDD (i.e., AVDD and DVDD) of ADS1292 and its GND and then measuring the current.

3. For testing the power-down current, I have soldered PWDN pin to GND on the board. Which mean, upon powering up, the PWDN pin will remain LOW indefinitely.

Note that initially, we see a higher power-down current (e.g., 100uA) and then the current appear to slowly drop down to less than 1uA as time progresses. The problem is it takes several seconds for the current to drop to 1uA.

Notes -

1. We are not supplying any clock to ADS1292 (CLKSEL pin is set to VDD). 

2. We are not doing any SPI register reads/writes

3. We are not applying any external references.

Hi,

"Note that initially, we see a higher power-down current (e.g., 100uA) and then the current appear to slowly drop down to less than 1uA as time progresses. The problem is it takes several seconds for the current to drop to 1uA."

As mentioned, 

"If PWDN/RESET is held low for longer than 2^9 fMOD clock cycles, the device is powered down."

"if 2^10 clock elapses it is powered down."

And, what you are seeing is about correct as discussed in other thread -

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1077819/ads1292-ads1292-power-down-current---need-clarification

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1077461/ads1292-unable-to-power-down-ads-1292

Thanks

Sorry, I did not understood.

(1) The datasheet says ADS1292 power downs after 2^9 fMOD clock cycles. 

According to https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1077461/ads1292-unable-to-power-down-ads-1292 the fmod is 128KHz. Which means the device will be powered down within 2^9 * 1/(128KHz) = 4ms. However, we see that it takes several tens of seconds for the power-down current to drop near to 1uA.

(2) As already mentioned, we are not doing any register read/writes. Can you confirm that we can put ADS1292 to power-down by just pulling down PWDN pin. ? Is any register read/write required ? (Note - we are not providing any external voltage reference or clock. Please see the schematic in the first post)

Hi,

For, "(2) As already mentioned, we are not doing any register read/writes. Can you confirm that we can put ADS1292 to power-down by just pulling down PWDN pin. ? Is any register read/write required ? (Note - we are not providing any external reference or clock. See the schematic)"

Yes, 

"If PWDN/RESET is held low for longer than 2^9 fMOD clock cycles, the device is powered down."

"if 2^10 clock elapses it is powered down."

Thanks.

2^10 clock cycles is only 4ms. So the device should be powered down within 4ms. However we see that the power-down current is around 100uA for several seconds before it slowly drops to 1uA. Can you please escalate this issue to the right team. ? We want to know why it takes ADS1292 several seconds to go to power-down.

Hi,

It could be several capacitors are still discharging, which leads to the long discharging(delay) time.

Thanks.

Can you help us determine which capacitors would be problematic and how to fix their values to ensure that the power-down current drops to 1uA within few milliseconds.

Hi,

Several things you could try.

For example

1. May I ask why the C31, C32 are 22uF and 10uF? Datasheet suggests 1uF or smaller.

2. Try reduce C51 to C54 one by one and see whether removing any of these could help.

But, please also watch/monitor the measured/acquired signal at the same time as this could affect the signal integrity.

Thanks

(1) There is a typo in the schematic. C31 and C32 (VCAP1 and VCAP2 capacitors) are 1uF. I have mentioned this as a "Note" in the first post. Do you suggest us to decrease their values to lower than 1uF ?

(2) How does reducing C51 and C54 help ? They are bypass capacitors to supply pins AVDD and DVDD. I expect the voltage across these capacitors to remain the same even during power-down.

Hi,

(1) Then, you may keep them as 1uF.

(2) Not sure whether it will really help, but it's something to try as the datasheet doesn't provide further information regarding to the power down delay time.

Thanks

I understand that datasheet of ADS1292 does not provide the time it takes for the current to go down to 1uA after driving the power-down pin low. For our project, we want to know this time. Can you please get this information from the designers of the IC? 

Hi,

May I ask for more clarification -

1. When you say "AVDD and DVDD are shorted. We are connecting supply to VDD (i.e., AVDD and DVDD) of ADS1292 and its GND and then measuring the current."

     How exactly the current is measured? Is any current meter used/put in series between any two nodes?

2. What might be the VDD voltage used?

3. One more thing to try might be see if it's possible to pull the CLKSEL to low when or after you power down?

Please allow us more time to get back to you.

Thanks

(1) We are using an ammeter in series to measure the current drawn by ADS1292 from the supply. The current measurement setup is verified. I do not see any issue in the way we measure the current. We also used source meter to measure current, we get similar power-down current results with source meter also.

(2) We use a 3.3V for VDD

(3) In the PCB, there is no provision to pull the CLKSEL pin to LOW. We hardwired the CLKSEL pin to VDD to use the internal CLOCK of ADS1292. We followed the datasheet guidelines in doing so.

Please get back to us at the earliest. Thank you for your time and patience.

Thanks.

Please allow us more time to have internal discussion.

Hello,

Is there an update ?

Hi,

Sorry for the delay, we still need more time for internal discussion.

Please allow us another 24 hours to get back to you.

Thanks

Hi,

After discussing with other engineers, we have some question and suggestions- 

1. Do you keep the VDD on&supplying when and after you pull down the /PWDN|/RESET pin?

2. We think the power down delay may due to any internal and/or external capacitance, so we may still suggest to try remove C30~32 and C7 one by one to see whether this power down delay time reduces.

Thanks