• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 46 subscribers
  • Views 248 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC122S021: Reset using /CS Pin?

PY (Pengyu) Song
Expert 5860 points
Part Number: ADC122S021
Other Parts Discussed in Thread: ADC122S051, ADC122S101

Hi team,

There is application that ADC122S021 is used with /CS pin low for continuous conversion, but can customer use /CS pin to reset ADC, i.e. to toggle /CS pin to start a fresh conversion? 

If no, is there any other method to reset ADC122S021 (without power reset)?

If yes, how long is needed to pull /CS pin high to reset the ADC? 

 

One more question, is effective sample rate always 1/16 of fsclk due to throughput is 16 SCLK cycles? 

  • ADC122S021 with 50-200ksps sample rate has fsclk specified at 0.8-3.2MHz - 16x times
  • ADC122S051 with 200-500ksps sample rate has fclk specified at 3.2-8MHz - 16x times
  • ADC122S101 with 500-1000ksps sample rate has fclk specified at 8-16MHz - 16x times

  • +1
    TI__Guru**** 171206 points

    Hi Py,

    I am hesitant to use the word 'reset' without fully knowing the context of your query.  If the intention is to re-start a conversion or re-synchronize SDI to SDO, then yes, raising /CS would accomplish that.  The minimum high time would be one SCLK period.  If the ADC122S021 is 'stuck' and not responding to SDI at all, it may require a power cycle to recover.

  • 0 in reply to Tom Hendrick
    TI__Expert 5860 points

    Hi Tom,

    Thank you. Do you see any problem/issue with ADC122S021 used with /CS pin always low? Datasheet has stated such usage, i.e. continuous conversion. 

    One more question, is effective sample rate always 1/16 of fsclk due to throughput is 16 SCLK cycles? 

    • ADC122S021 with 50-200ksps sample rate has fsclk specified at 0.8-3.2MHz - 16x times
    • ADC122S051 with 200-500ksps sample rate has fclk specified at 3.2-8MHz - 16x times
    • ADC122S101 with 500-1000ksps sample rate has fclk specified at 8-16MHz - 16x times

  • +1 in reply to PY (Pengyu) Song
    TI__Guru**** 171206 points

    Hi PY,

    There is no issue with leaving /CS low.  Yes, the sample rates shown in Table 1 are all based on fSCLK/16 (MAX), which assumes the /CS is held low and the SCLK is continuous.