Hi Support Team,
Correct me if I'm wrong, but the only way to have 2MSPS with ADS1675 is with the following settings:
Fclk = 16 MHz
DRATE = 101 => Fclk/8 = 2MSPS
With DRDY timing = 1/2MSPS = 0.5 us
and Fsclk = 16Mhz x 3 = 48 Mhz, which give me a correct 48 Mbit/s (2x24 bit, so 2MSPS) with one sclk pulse for one data
If I stay with Fclk = 32 Mhz
DRATE = 100 => Fclk/16 = 2MSPS
DRDY tuming remain 0.5 us
but Fsclk = 32 MHz x 3 = 96 MHz ... this would mean that I will have 2 clock pulse for one bit data ?
Thanks
Andrea