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DAC5688: CLK2/CLK2C LVDS or LVPECL

Part Number: DAC5688
Other Parts Discussed in Thread: LMK04828

Hi Team,

(1) Does CLK2/CLK2C accept LVDS? Or is LVPECL only available?

(2) For LVPECL, I want to confirm how to set the clock interface. Per datasheet, it looks : 

- VCM = CLKVDD 1.8V * 2/3 = 1.2V

-  1V swing

- supply voltage should be 3.3V domain

Is it correct?

Is the circuit configuration correct?

Sincerely,

Ella

  • Hi Ella,

    Regarding your question 1

    (1) Does CLK2/CLK2C accept LVDS? Or is LVPECL only available?

    It is best to use LVPECL or HSDC driver (on the LMK family) to yield the best slew rate and also the best jitter/phase noise performance. Please discuss this with the clocking team on the type of clock drivers that yield the best phase noise for the DAC5688.

    Regarding your question 2

    (2) For LVPECL, I want to confirm how to set the clock interface. Per datasheet, it looks : 

    Different clock drivers and swing settings have different interface on the LVPECL pull-down. For example, LMK04828 has the following network for LVPECL termination. 

  • Ella,

    Regarding the LVPECL to LVDS termination:

    • An LVPECL driver is a current driver, which means it requires a DC current return path to ground. Emitter resistors (the resistors pulled-down to ground) can be 140-220 ohms depending on the desired swing and common mode. For standard LVPECL, 150 ohms is used.
    • An LVDS receiver/driver is a current driver which requires a 100 ohm differential termination to generate the waveform.
    • To convert from LVPECL to LVDS, two specs must be accounted: LVDS receiver input swing and common mode voltage requirements (as you have listed).
      • Place 150 ohms on the driver side to provide the necessary termination for the LVPECL driver.
      • Place AC-coupling caps after the 150-ohm termination to clear the common mode voltage set by the LVPECL driver. For standard/typical, LVPECL common mode voltage is VCC-2 V and LVDS is 1.2 V.
      • After the AC-coupling caps, the common mode must be reset through a resistor network (voltage divider) to get 1.2 V. 
        • Note: This resistor network should not be placed when the LVDS receiver is internally DC biased. In your case, the DAC is not internally biased and therefore, must include the resistor network to set the common mode.
      • Finally, put the 100-ohm differential termination as close to the receiver as possible to provide the necessary LVDS termination.
    • Some examples: 

    Regards,

    Jennifer

  • Hi Kang, Jennifer,

    Thank you for reply. I'm confused. Kang mentioned that CLK2/CLK2C does not accept LVDS. Why do we need LVPECL to LVDS termination as Jennifer mentioned? 

     

    For example, LMK04828 has the following network for LVPECL termination

    The capture you shared is showing the driver side termination. How should the receiver side termination look like?

    I'm not familiar with this application. So I hope your kind and patient understanding to consolidate a proper feedback for customer.

    Sincerely,

    Ella

  • Hi Ella,

    No worries. The DAC5688 clk receiver requires 100ohm termination at the CLK2p/m pins. It is shown on the pictures shared by Jennifer above.

    -Kang

  • Hi Kang, Jennifer,

    Thanks. Let me have additional questions!

    1) For figure 40 (LVPECL input for CLK2/C), how do we set the common mode voltage 1.2V? For LVDS, we need to put resistor network for DC bias as you mentioned above. 

    2) Customer can feed LVPECL to CLK2/C. Figure 40 illustrates the configuration for LVPECL but I'm confused.

    - 150ohm to GND should be placed on driver end. Does receiver (CLK2/C of DAC5688) also require this current driving resistor?

    - 100ohm termination is for LVDS. LVPECL also requires this 100ohm termination?

    Thanks!

    Ella

  • May I have one more question?

    3) I looked at AN-1194 Failsafe Biasing of LVDS Interfaces (Rev. C) (ti.com). Does DAC5688 provide internal failsafe biasing for open input conditions? Customer wants to know the difference between two LVDS DC bias configuration that Jeniffer showed earlier. If it has internal failsafe biasing, customer doesn't necessarily go with first option. Right?

    Ella

  • Hi Ella,

    Let me reply tomorrow.

    Regards,

    Jennifer

  • Ella,

    I looked into the DAC datasheet more--there is 1.2 V internal bias which means the resistor network is not required and you can follow Figure 40 as is.

    To answer your past questions in detail for future reference:

    1) For figure 40 (LVPECL input for CLK2/C), how do we set the common mode voltage 1.2V? For LVDS, we need to put resistor network for DC bias as you mentioned above. 

    • [JB] You can add a resistor network after the AC caps on the receiver side, like the one I shared previously (Rtop = 13k ohms and Rbottom = 7.5 k ohms) to set the VCM = 1.2 V. Note this was only if the receiver is not internally biased. The math works out as follows: 
      • VCM =  Vcc * Rbottom / (Rtop + Rbottom) 
      • VCM = 3.3 * 7.5k/ (13k+ 7.5k) 
      • VCM = 1.20731707 V = ~1.2 V

    2) Customer can feed LVPECL to CLK2/C. Figure 40 illustrates the configuration for LVPECL but I'm confused.

    • [JB] When translating between two signal formats, you can break the termination scheme into two basic pieces: termination on driver and termination on receiver side. Let's consider a general example:
      • Driver Side
        • Bullet 1: Here, you should provide the termination required by the driver. For LVPECL, you place the 150 ohms to GND.
      • Receiver side
        • Bullet 2a: AC-caps
          • Here, you place the AC-caps to "clear" the common voltage. In other words, the common voltage measured at Bullet 1 will be different from the common voltage measured at Bullet 2b. You can think of VCM = 0 V at Bullet 2a where the caps are.
        • Bullet 2b: Termination, receiver side
          • Here, you place the termination required by the receiver (e.g. 100 ohm differential for LVDS).
          • You also place a resistor network if you need to set the common voltage. For example, if the Driver has VCM = 1.3 V, we place AC caps to make VCM = 0V, then we add resistor network to set VCM = 0.6 V.

    - 150ohm to GND should be placed on driver end. Does receiver (CLK2/C of DAC5688) also require this current driving resistor?

    • [JB] The 150 ohm to GND are on the driver end to satisfy the LVPECL driver requirements.
    • The DAC receiver does not require the 150 ohm resistors. The reason why we would change signal type is because
      • a) the receiver requires that specific signal type (e.g. the receiver topology is LVDS based, accepting LVDS only) or
      • b) the receiver has a specific VCM / swing requirement that the driver does not meet.  For example, LVPECL has larger swing than LVDS. Some receivers can't handle the LVPECL swing input and must be attenuated, which is why we must translate from LVPECL to LVDS. 

    - 100ohm termination is for LVDS. LVPECL also requires this 100ohm termination?

    • No.