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ADS54J60EVM: Deterministic Latency Design with ADS54J60, Xilinx VC707 Board and TI JESD204B Verilog Reference Design

Lin Ma
Prodigy 20 points
Part Number: ADS54J60EVM
Other Parts Discussed in Thread: ADS54J60, , DAC39J84

Hi, 

I am working on deterministic latency design with ADS54J60 board, VC707 board, and Verilog code based on JESD204B reference design provided by TI. 

I could get the sampled waveform from the ADC, but I cannot get deterministic latency.

On the FPGA side, I followed all the steps described by the TI JESD204B reference design documents, and modify my Verilog codes accordingly. But still, deterministic latency is not achieved (I send a pulse to the ADC and check the delay from sending to FPGA receiving, this overall delay varies a lot).

I think the bug is on the ADS54J60 side. Could you give me a sample configuration file with deterministic latency for the ADS54J60 EVM board, such that I could upload it to the board and have a test?

Thanks,

Ma Lin 

  • 0
    TI__Guru* 91947 points

    Ma,

    If using the TI ADS54J60EVM, try these two files. This will set the ADC to use a LMFS = 8224, K = 16  and a sample rate of 983.04MHz.

    Regards,

    Jim

    4857.ADS54J60_LMF_8224.cfg6758.LMK_Config_Onboard_983p04_MSPS.cfg

  • 0 in reply to jim s
    Prodigy 20 points

    Hi Jim,

    Thank you! Will This two files ensure deterministic latency for the ADC-JESD-FPGA signal path?

    We can get the sampled signal, but we cannot achieve determinisitc latency. The test setup is described as below: we generate a pulse on the FPGA, send this digital pulse to TI DAC39J84 through JESD204B, DAC generates the analog pulse, this pulse is then directed to the ADS54J60, then ADC quantizes the pulse and send it back to FPGA through JESD204B, then on the FPGA, we calculate the overal signal propagation delay. This delay number is not fixed. 

    On the FPGA side, we use the JESD204B reference design provided by TI as well.

    in addition to the ADC config file, is there any other place I should check to get the deterministic latency, or the constant signal propagation delay?

    Thanks again for your great help on this.

    Thanks,

    Lin

  • 0 in reply to Lin Ma
    TI__Guru* 91947 points

    Lin,

    With the ADS554J60 set to use subclass 1 mode, the output should always be deterministic if all other parameters are correct. Have you tried to use a different value for RBD in the TI JESD204C IP? You also may want to try using a large value for K.

    Regards,

    Jim