DAC7760: Occasional SPI Failure: DAC7760 reads an extra 0 bit between address byte and first data byte

I think the DAC7760 returns the user calibrated value when you read the DATA register. I don't see this documented. The closest hint is a mention under Programmable Slew Rate: "If the DAC data register is read while the DAC output is still changing, the instantaneous value is read."

Update Gain:  1.20  b353
#### registers before gain update
DAC  Ctl: 1001  Cfg: 0320  Gain: 8000  Zero: 0000  Status: 0000  Data: 0ff0
#### registers after gain update
DAC  Ctl: 1001  Cfg: 0320  Gain: b350  Zero: 0000  Status: 0000  Data: 1320
DAC DATA write failure 0ff0 ==> 1320
DAC DATA write failure 0ff0 ==> 1320
...

0x0ff = 255
255 * 1.2 = 306
306 = 0x132

Also, the data sheet doesn't mention that gain and zero offset unlike the DATA register are 16 bit values with the least significant nibble masked. Notice that a written gain of 0xB353 results in a gain register of 0xB350. I guess that internally, it's all 16-bit, and that DATA is really a 16-bit number with a size 16 step between values on the DAC7760 resulting in an effective range of 12 bits.

I think the "extra inserted" zero bit is the default gain, 0.5, applied to data values. A divide by 2 is a right shift of one bit.

• Gain is a 16-bit unsigned number where 0x0000 = 0.5x and 0xFFFF = 1.5x. The least significant 4 bits are zeros.
• Zero is a 12-bit signed number stored in the most significant 12 bits of a 16-bit register.
• Data
  • WRITE: the desired, un-calibrated setting
  • READ:
    • the current value if slewing
    • if slewing disabled, the calibrated setting, i.e. setting * gain + zero
    • the value after calibration cannot exceed the register range
      • you can't make the bottom of the range go lower with a negative offset
      • so, an offset of 0.1 will output Range_Min + 0.1
      • but, an offset of -0.1 will read Range_Min because Range_Min + (-0.1) is below Range_Min
      • a negative offset will apply for larger values, though
      • all of the above is empirical from testing

Hi Harvey,

Joe will review this and respond on Monday.

Thanks,

Paul

Thanks for the confirmation. I found it helpful to describe the calibration parameters like this:

• zero: signed 12-bit (shifted 4 bits left in a 16-bit register)
  • -2048...2047
• gain: unsigned 16-bit (least significant 4 bits masked) mapped to 0.5...1.5
  • 0...65535 in steps of 16

Related, follow-up question:

In 4-20mA mode, how does one correct for the chip falling short of the endpoints?

Example1:

• Gain=1.0, Zero=0.0, CODE_OUT=0
• Chip reads 4.01mA. So, we want to apply a negative zero offset, but it has no effect because after the math, the number is clamped to a CODE_OUT of 0...4095. So, 0 - Offset is still 0.

Example2:

• Gain=1.0, Zero=0.0, CODE_OUT=FFF  (12-bit 7760 values)
• Chip reads 19.85mA. So, we want to boost the gain, but it's the same situation as before. FFF * 1.x is still FFF.

How do I solve for this?

Thanks, that's the conclusion I reached as well. I'll ask if its more important to have resolution or accurate endpoints.