Hi Team,
Our customer needs help with ADC3661 configuration. Please see the details of his inquiry below.
I need register load sequence to configure ADC3661 analog to digital converter to 2-wire interface in bypass mode.
I can copy the values of the registers that I tried to change to achieve the desired configuration (2-wire interface in bypass mode)
if(adc_reset == 1'b0) begin //load //0x07 register value=0x4B if (cnt <= 24) begin c_spi_cs <= 1'b0; c_spi_config_done <= 1'b0; configreg7 = configreg7 << 1; c_spi_sdo = configreg7[24]; end // wait if (cnt > 24 && cnt<= 28) begin c_spi_cs <= 1'b1; c_spi_sdo = 1'b1; c_spi_config_done <= 1'b0; end // load 0x13 register value=0x00 if (cnt > 28 && cnt<= 52) begin c_spi_cs <= 1'b0; c_spi_config_done <= 1'b0; configreg19r = configreg19r << 1; c_spi_sdo = configreg19r[24]; end // wait 1 ms if (cnt > 52 && cnt<= 556) begin c_spi_cs <= 1'b1; c_spi_sdo = 1'b1; c_spi_config_done <= 1'b0; end // load 0x13 register value=0x01 if (cnt > 556 && cnt<= 580) begin c_spi_cs <= 1'b0; c_spi_config_done <= 1'b0; configreg19s = configreg19s << 1; c_spi_sdo = configreg19s[24]; end // wait if (cnt > 580 && cnt<= 584) begin c_spi_cs <= 1'b1; c_spi_sdo = 1'b1; c_spi_config_done <= 1'b0; end // load 0x19 register value=0x10 if (cnt > 584 && cnt<= 608) begin c_spi_cs <= 1'b0; c_spi_config_done <= 1'b0; configreg25 = configreg25 << 1; c_spi_sdo = configreg25[24]; end // wait if (cnt > 608 && cnt<= 612) begin c_spi_cs <= 1'b1; c_spi_sdo = 1'b1; c_spi_config_done <= 1'b0; end // load 0x1B register value=0x88 if (cnt > 612 && cnt<= 636) begin c_spi_cs <= 1'b0; c_spi_config_done <= 1'b0; configreg27 = configreg27 << 1; c_spi_sdo = configreg27[24]; end // wait if (cnt > 636 && cnt<= 640) begin c_spi_cs <= 1'b1; c_spi_sdo = 1'b1; c_spi_config_done <= 1'b0; end // load reference selection buffer 0x0E register value=0x0E if (cnt > 640 && cnt <= 664) begin c_spi_cs <= 1'b0; c_spi_config_done <= 1'b0; configreg14 = configreg14 << 1; c_spi_sdo = configreg14[24]; end
That is a piece of Verilog code that loads registers. I know that the SPI interface from the FPGA works correctly because I can decode SPI traffic using a logic analyzer.
Also, I put in comments value of the registers and how long I wait.
The spi clock frequency is 500kHz (that is well in the range given by the datasheet).
Also, I noticed some typos in the datasheet where the detailed information about registers is provided.
configreg7 = 25'b0_0000_0000_0000_0111_0100_1011; //0x07 register value=0x4B configreg19s = 25'b0_0000_0000_0001_0011_0000_0000; // 0x13 register value=0x00 configreg19r = 25'b0_0000_0000_0001_0011_0000_0001; // 0x13 register value=0x01 configreg14 = 25'b0_0000_0000_0000_1110_0000_1000; // 0x0E register value=0x0E configreg7_IF_en = 25'b0_0000_0000_0000_0111_0100_1011; //0x07 register value=4B configreg25 = 25'b0_0000_0000_0001_1001_0001_0000; //0x19 register value=0x10 configreg27 = 25'b0_0000_0000_0001_1011_1000_1000; // 0x1B register value=0x88
Binary values of the registers
The error is in Table 8-26 Description for Bits5-6 (MAPPER EN bit (D6)) it should be D7.
Also, When the register write is in progress should be a sample clock running (pins 6 and 7) I tried both ways but it did not produce any difference. I am aware of the calibration requirement which takes of 200000 cycles of the sample clock.
Also, we want to use the internal reference which is visible from the register writes
The REFBUF pin is pulled up to AVDD and we use a differential sample clock with connections described in the datasheet on page 33.
Regards,
Danilo
