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ADS54J66: Regarding LMFC boundary of ADS54J66

sarojini ravi
Prodigy 110 points
Part Number: ADS54J66

Hi,

I am using ADS54j66 ADC. I have an requirement multi chip synchronization. it was achieved by JESD204b subclass 1.

two adc's are mounted in the board.

Following are JESD204B parameters.

No of lanes                  L = 4

No of convertors             M = 4

Octets per frame             F  = 2

Frames per multiframe        K = 16

Samples per frame            S = 1

Sampling clock                 = 300Mhz

Frame clock                    = 300Mhz


To find the LMFC boundary of ADS54j66, i intentionally added the delay in one of the Convertor SYNC pin.

when ever sync pin delay across the ADC exceeding one LMFC boundary,  i was expecting  16(Frames per multi frame) frame clock delay in ILA sequence.

But it was observed 32 frame clock delay in ILA Sequence across the ADC.

when LMFC count in the ADC(ADS54J66) will wrap to zero ?  If it is Frames per multi frame i should get 16 frame clocks delay in ILA.

Kindly clarify.

Thanks in advance.

Regards,

Sarojini




  • 0
    TI__Guru* 91947 points

    Sarojini,

    Are you delaying SYNC or SYSREF? Can you send a timing diagram to show what exactly what you are seeing? How much is the delay? If you are delaying SYNC, are you using both SYNCbAB and SYNCbCD for each part? Why are you adding this delay? Are the two parts not synchronized? Do both parts have the SYSREF and device clocks all routed with the same trace length? 

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 110 points

    Hi jim,

      I am delaying the SYNC.Sysref for both the ADC was synchronized. We are used SYNCbAB pin. We have achieved the synchronization between ADC.

    All our SYSREF and Device clock having same trace length.

    Since we are going to synchronize multiple boards ,We want to know the LMFC boundary of ADS54J66.

    I want to assert the SYNC pulse in middle of LMFC boundary. So all the ADC ILA we will get in single LMFC boundary.

    When LMFC count in the ADC(ADS54J66) will wrap to zero ?  If it is Frames per multi frame i should get 16 frame clocks delay in ILA.

    Regards,

    Sarojini

  • 0 in reply to sarojini ravi
    TI__Guru* 91947 points

    Sarojini,

    What is your RBD setting? Have you tried this test using K = 20 or 32? Is your SYNC synchronized with SYSREF? How is SYNC asserted? Normally this is not synchronized with anything.

    Regards,

    Jim

  • 0 in reply to sarojini ravi
    TI__Intellectual 1570 points

    Hi Sarojini,

    Please confirm the lane rate. I am assuming your JESD IP is export 32 bits per lane?

    Regards,

    Ameet

  • 0 in reply to jim s
    Prodigy 110 points

    Hi jim,

     Now My RBD is 0. We only tired K =16. Based on sysref sync will be asserted to both convertors. 

    • Just I want to know about LMFC boundary when LMFC will wrap yo zero. 

    Regards, 

    Sarojini

  • 0 in reply to Ameet Bagwe
    Prodigy 110 points

    Hi Ameet,

    My lane rate is 6 Gbps. From JESD IP is exporting the 16 bits per lane per frame clock.

    Regards,

    Sarojini

  • 0 in reply to sarojini ravi
    TI__Intellectual 1570 points

    Hi Sarojini,

    The LMFC boundary of the ADC will be the positive edge of the device clock that samples a change of 0->1 on the SYSREF. 

    In the scenario that you have mentioned, it is possible that the ADC is carrying out an extra multi-frame of synchronization on the SYNCn pin, which is why you are seeing a two multi-frame delta when the SYNCn delay pushes it into the next LMFC period. This, however, will not impact synchronization across ADCs, because the samples will not see an additional delay. 

    Regards,

    Ameet