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AMC7832: SPI communication problem

S.G.
Prodigy 40 points
Part Number: AMC7832

Hello TI Team,

I am trying to communicate with an AMC7832 chip with an emulated spi protocol over JTAG.

The boundary scan vectors are changing rather slow in respect to a properly clocked spi protocol but I am able to read registers correctly either in stream or individualy.

The problem seems to be that I cannot write to any register. I tried to write on interface config 1 so to enable single instructions but when I read back I get the default values. This also happens with all registers.

On the datasheet the information is not clear but I presume write bit is '0' and read bit is '1' on both single and stream operations. Could you confirm?

Also does the AMC7832 has maximum timing requirements for spi communication?

Thank you.

  • +1
    TI__Guru 53163 points

    Hi S.G.

    You are correct, the write bit is 0.  There are not really any maximum timing limits, this device would respond even with very, very slow SPI clocks (Hz).  I recommend that you capture a write command using an oscilloscope or logic analyzer and ensure that the clock phase and polarity is correct and matches the device. This is usually the issue.  You could also try writing to one of the ADC Mux registers with some unique value (e.g. 0x55) and read that back.  I suggest this register as it is an independent function in the device.  The readback will reveal if you have some kind of bit shift, which is indicative a clock issue.  The scope is the best method.

    Thanks,

    Paul

  • 0 in reply to Paul_Frost
    Prodigy 40 points

    Hi Paul,

    Thank you for the information. I was able to write to an ADC mux register with a very slow single vector.

    Apparently there problem might be on implementation of the write register command in the boundary scan vector and/or the speed of the running test.

    I have a related question to this subject and the bit shift you mentioned.The AMC7832 is connected to an fpga through digital Isolators. The SPI commands are passing through two ISO7762F isolators. The nCS/SCLK lines on one isolator and SDI/SDO on a second isolator. Do you think this might create a clock issue? 

    Kind regards

    Spyros

  • +1 in reply to S.G.
    TI__Guru 53163 points

    Not likely, the isolators likely only a few 100ns of delay, if that.  I think it is more likely your have some kind of clock phase or polarity issue.  I recommend you investigate with a scope.

  • 0 in reply to Paul_Frost
    Prodigy 40 points

    Hi Paul,

    Thank you for the information. Problem is pretty much resolved as far as Hardware is concerned. I will investigate the software issues further.

    Kind regards

    Spyros