Other Parts Discussed in Thread: AFE5832LP,
Dera all,
We have purchased TX7332EVM and AFE5832LP EVMs for our FPGA development. We plan to use the FPGA to trigger the TR_EN and sync signals on TX7332EVM. Can we achieve this by grounding the CPLD clock and connecting SYNC_TP and TR_EN1 test points to the FPGA IO port? Additionally, is it possible to control all output ports through the FPGA?
Best regards,
Rouzbeh