Hi All,
I am driving DAC39J84EVM using an external clock (with TSW14J56 Rev E board as the generator and using HSDC Pro for software support.) For this purpose, I am providing a 600 MHz external clock (sine pulses) using signal generator (oscilloscope). I am providing this clock to CLKIN SMA connector (J17) on the board. After this I run the DAC GUI in external mode, and generate a 10 MHz sine pulse using I/Q generator on HSDC Pro (screenshot attached). When I set the number of Ser Des Lanes as 4 and interpolation as 1 on the DAC GUI, I am able to get the signal out with minimal distortion. However, when I set the number of SerDes Lanes as 8 and interpolation 1, I get a distorted pattern out ( screenshot attached for both the pattern and setting on GUI).
Are there any other modifications to be done to make the 8 SerDes lanes settings work, because when we go to higher clock frequencies ( our requirement is 1 GHz), the only available setting is 8 SerDes lanes ( as for 4 SerDes lanes, the SerDes Linerate becomes greater than accepted limit of 12500) and therefore we require the 8 SerDes Lanes settings to work.
Thank for your consideration and help.
Thanks and Regards,
Vaibhav Jain.
