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Hey,
Just want to confirm the LVPECL clock input levels.
Also, what are the AC coupled LVDS clock input levels (figure 35)? If I understand correctly, 0.8V - 1.6V per "LVDS INPUTS: DIGITAL INPUT DATA" section
Cameron,
The LVPECL differential voltage needs to be at least 200mV and typical 1V. The LVDS inputs are typically 200mV differential swing with a common mode voltage of 1.2V.
The LVDS INPUTS: DIGITAL INPUT DATA section in the data sheet is for the digital data lines D[9..0], not the input clock.
Regards,
Jim