Other Parts Discussed in Thread: DAC5675A
Hello,
We are currently using the DAC5675A (on our prototype) and DAC5675A-SP is set to be installed on the flight model. Both of these are currently planned to be used with a Virtex-5, which is currently driving the clock lines with an LVDS signal. It has been used this way for previous flight projects with seemingly no issues that I am aware of.
We have been testing it pretty regularly on our prototypes with seemingly no issues at the moment. We are running it at 144 MHz, the expected temperature range will be from -40 C to +90 C during flight. (Though we haven't done temperature testing yet).
I wanted to touch base with TI on a couple of items:
- I understand that the DAC5675A is expecting LVPECL signal levels, what would we see at the output if the clock was dropping below the voltage needed to run the clock lines on the DAC? I assume maybe some dropped samples and the output would look qlitchy?
- Considering this has worked well for the prototypes that we built, would we expect the DAC to require a higher or lower voltage on the clock lines across temperature? If we assumed that the LVDS voltage levels we have at ambient stayed the same, would we expect the DAC to be able to work with them across temperature?
- Is driving the clock lines with a lower voltage signal going to result in decreased performance? Assuming all the samples still get clocked in, does the act of just having the clock signals lower than the 0.4 V have an impact on performance?
- Is there a hard cut off that is known for the DAC5675A Clock lines? Would you expect it to work under the 0.4 V at all? Or is it something that might vary from component to component?
Thanks,
Brandon
