Other Parts Discussed in Thread: DAC39J84, LMK04828
Hi Team,
A customer purchased a few evaluation boards DAC39J84EVM for prototype development. However, they found that one of the boards was defective and failed to lock to triggers.
The cause of the issue was identified was a defective crystal oscillator here is the details of the problems encountered:
On DAC39J84 evaluation board have a 122.88MHz CVHD-950 VCXO connected to LMK04828 OSCin. the customer connected an ideal 100MHz clock input to J17 CLKIN and configured the LMK04828 PLL1 Clkin1 R divider to 1250, N divider to 1536. This configuration should allow LMK04828 PLL1 to lock and ensure synchronization across all DAC EVM boards. However, despite all other evaluation boards PLL1 successfully locked, the particular board in question PLL1 failed to lock thus cannot synchronize to the same clock domain. They have tried several different ideal 100MHz clock inputs but the issue persists. Based on the datasheet the VCXO should have a tuning range of 10kHz, since their external clock input is accurate enough and all other DAC EVM board work, they conclude that the VCXO on this board may not be accurate.
Would you kindly confirm this?
Thank you and regards,
Marvin
