ADC3422: PRBS generator of test data for LVDS interface

Hi Andrea,

Here is the feedback I got from the design team:

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The PRBS sequence is tapped from a 23 bit LFSR with a polynomial 1+x^18+x^23. Here is the update equation and seed that generates the LFSR

Update Equation – LFSR_next = (LFSR << 1) | (LFSR[17] ^ LFSR[22]); (<< denotes left shift of 1, ^ denotes XOR operation)

Seed – 2**23 – 1 (i.e., all bit positions are 1)

Output pattern – LFSR[15:2] (i.e., bit positions 15 down to 2 are tapped and sent out as test pattern)

Please Note:

1. The internal LFSR is not synchronously reset. Hence, the start point after reset release could be ambiguous and might change across power cycles / resets. There is no guarantee on the phase relation.
2. Toggle pattern might be a better option for “in circuit testing” as the ambiguity is just 1 clock cycle.

We would recommend that you use the toggle pattern for testing - PRBS may be complicated because of the phase ambiguity.

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Regards, Amy