ADS1292R: Using internal clock, how to determine maximum SPI TSCLK speed?

Hi, I'm trying to understand the SPI clock speed (TSCLK) that I can configure for the ADS1292R chip. 

According to Tsclk FAQ, it seems that we can reach up to 20MHz for the Tsclk. 

However, in chapter 8.5.1.2 of the datasheet (chapter Serial Clock (SCLK)),

It was stated that SCLK can only be twice the speed of f_clk?

In our application, we are configuring it with a 4 MHz SPI speed. We used the chip's internal clock (512KHz) and configured the sampling rate at 4000 samples/second. 

Throughout our tests it seems that the signal output is okay and does not have any issue with the current SPI settings. However, after we re-read the datasheet, we just wanted to make sure if by using 4MHz would pose any issues?

How to correctly determine the speed of the Tsclk then? And is it correct to assume that the denominator of equation 9 is divided by 72?

Thanks!