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ADC082S021: Result is multiplied by 2 - CS timing question

Darren Jenkins
Genius 10536 points
Part Number: ADC082S021

ADC team,

Our customer is using ADC082S021 and seeing digital results that are twice the expected value, but only on one of the two channels.

I'm looking at some logic analyzer captures to check CS and CLK timing.  They have the MCU configured for CLK staying low between messages.  When the Read ends, and CS goes high, the clock has just finished its 32nd pulse, meaning it has gone high then low before CS goes high.  Is this acceptable?  

I don't see a spec that requires the clock be high when CS goes high, but the image in figure 5 of the datasheet looks that way.  Is there are requirement?

Thanks,
Darren

  • 0
    TI__Expert 4070 points

    Hi Darren,

    Thanks for your question!

    In the datasheet, the section about "Using the ADC082S021" mentions that it is "best to strictly observe the minimum tCSU and tCLH times given in the Timing Specifications" otherwise there may be a DIN delay.

    The tCSU and tCLH time definitions are shown in the figure 5 and the timing specifications are mentioned in the table below:

    It would also be helpful to see what your results/timing diagrams look like to better understand the issue.

    I hope this helps!

    Best,

    Samiha