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ADS127L11: How to calculate the latency

Ruixin Feng
Intellectual 1765 points
Part Number: ADS127L11

Hi team,

customer test the latency of ADS127L11 and found the result is different from the data in datasheet. Customer used synchronized mode and use 25MHz as Fclk, 400ksps as data rate, OSR=32, Sinc4. According to datasheet, the latency is10.63us. But customer test result is 11.4~11.7us. They use oscilloscope to test the time between rising edge of Start and first falling edge of DRDY.

Questions are:

1.  How to calculate latency of every sinc filter?

2. Besides latency of sinc filter, is there any other factors will add latency ? 

3. If customer give START like figure 8-25 in datasheet, are the first latency and the second latency same time?

4. Is 11.4us reasonable? 

Thanks!

Rayna 

  • 0
    TI__Mastermind 36290 points

    Hello Rayna,

    The latency times in the datasheet assume f-CLK=25.6MHz.  When using a different f-CLK frequency, the latency time will linearly scale.

    1. Using the SINC4 filter, OSR=32, and 25MHz f-CLK, the actual data rate will be 400*25/25.6=390.625ksps, and the latency will increase by a factor of 25.6/25, or 10.63us*25.6/25=10.9us.  If using the internal pre-charge buffers, there is an additional delay of 8*(1/f-CLK), or 8*(1/25M)= 0.3us, so the total time will be 10.9+0.3=11.2us, which is very close to the customer measurements.

    2. Latency time increases 8 / fCLK (µs) when analog input buffers are enabled.  Also, there is a programmable Start delay to allow for external settling.  See the DELAY[2:0] bits of the CONFIG3 register for programming details.

    3. Yes, when the rising edge of START pin triggers a synchronization, the latency time will repeat; the first, second, third, and so forth latency times will be equal, or the same.

    4. 11.4us is a bit longer than I would expect using a 25MHz oscillator.  The customer may have a clock slightly slower than 25MHz, such as 24.9MHz.  The latency measurements may also be off as well.

    If the latency time is constantly changing, then they may not have a 'clean' clock signal at the CLK input pin of the ADS127L11.  I would suggest measuring the clock signal at the pin of the ADC using an oscilloscope and verify that it is a clean square-wave, with magnitude equal to IOVDD voltage supply. 

    Regards,
    Keith Nicholas
    Precision ADC Applications