DAC3283: Clock Input Standard Reg.

Deva Guru

Prodigy 205 points

Part Number: DAC3283

HI!

I am planning to use DAC3283 for the below application and i have the below query,

Application:

DAC CLK: 4000MHz

Output Freq: 75 MHz

Query:

1)I have only CML clock outputs in my system with VOD=420mVpp (typ). Is there a way to interface CML clock to DACCLKP/N inputs of DAC3283?

2) will there be any degradation in phase noise of the outputs? If so, how much?

Thanks in-advance,

Deva

over 1 year ago

0 Rob Reeder over 1 year ago

TI__Mastermind 23250 points

Hi Deva,

CML is one of the best interfaces to use in terms of lower phase noise.

This interface will work. The standard output differential is 800mVpp for CML which is in line of what the DAC's clock pins can accept.

Regards,

Rob

0 Deva Guru over 1 year ago in reply to Rob Reeder

Prodigy 205 points

Hi Rob,

I could find the below note in Datasheet,

" Driving the clock input with a differential voltage lower than 1V will result in degraded performance."

with reference to above, Will the voltage level of CML with swing of 800mVpp cause any impact on the performance of the DAC (interms of phase noise)? If so, what is the level of degradation to be expected?

Thanks in-advance,

Deva

0 Rob Reeder over 1 year ago in reply to Deva Guru

TI__Mastermind 23250 points

Hi Deva,

Thanks for bringing this to my attention.

Unfortunately, this is a very old device/DAC and we do not have this specific information.

Regards,

Rob

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DAC3283: Clock Input Standard Reg.