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ADC34J24EVM: Can I evaluate it with Xilinx FPGA

Jason Lee
Prodigy 75 points
Part Number: ADC34J24EVM
Other Parts Discussed in Thread: ADC34J24,

I have TI204C-IP and plannig to use ADC34J24 with Xilinx MpSoC+.

I'd like test the FPGA IP before my custome hardware come out.

My plan is using ADC34J24EVM and Xilinx ZCU102 EVB.

It looks like ADC34J24EVM has CPLD of which FPGA souce is not open to public.

I'd like to make sure that JESD204 communication is OK between ADC34J24EVM and Xilinx ZCU102 without the FPGA source?

And also I'd like to know whether the FMC connection between ADC34J24EVM and Xilinx ZCU102 is available.

Thank you in advance.

  • +1
    TI__Intellectual 1540 points

    Hi Jason,

    You should be able to test the ADC EVM with the ZCU102. Kindly use the ZCU102 reference design from the TI IP archive as your starting point and edit it for the following:

    1> Edit the jesd_link_params.vh file to make the IP type as "RX". This will eliminate the TX part. 

    2> Set the RX parameters in the jesd_link_params.vh file to match the ADC's JESD mode

    3> Edit the refdesign_rx.sv file to match the lane data to sample mapping based on the ADC's data packing

    4> Configure the transceiver xci file to meet the lane rate and reference clock settings for the EVM

    I don't believe that the CPLD source needs to be edited, but we will check within the relevant support team and revert on this.

    Regards,

    Ameet