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ADS131M04: Varying clock frequency

D M
Prodigy 10 points
Part Number: ADS131M04

Hello

 We are using the ADS131M04 to measure mains voltage (rms magnitude, phase and harmonic components via FFT). We want to make sure there are 256 samples per cycle (coherent sampling to minimise measurement inaccuracy). This requires the sampling rate/phase to follow the (slowly) varying mains input signal.

 When can the ADC clk input frequency be changed to ensure continuous ADC operation? Could it be related to the DRDY signal?

 The sampling rate needs to be known for each calculation period, the sampling rate is an integral part of the calculation.

 Is this the right part for what we want?

 Thanks

  • 0
    TI__Mastermind 18900 points

    Hey D M,

    D M said:
     When can the ADC clk input frequency be changed to ensure continuous ADC operation? Could it be related to the DRDY signal?

    The ADS131M0x follows the traditional architecture of a delta-sigma. The f_CLKIN derives the f_modulator which, through the OSR register, will calculate the f_data which is the same as f_DRDY signal.

    I haven't heard of a customer attempting to coherently sample the voltage mains before. I'm wondering if they measure the frequency and directly change the PHASE registers to achieve similar results instead.

    Anyways, I find that most will reset the digital filter when changing clock frequencies. That means you would need to wait for resettled data. I imagine you don't want to do that given the application so I'm wondering what will happen to the digital modulator if you attempt to do that on the fly.

    As far as I could tell, it should work but I need to talk with the team with any concerns there might be.

    Best,

    -Cole

  • 0 in reply to Cole Macias
    Prodigy 10 points

    Hi Cole,

    We have found this application note Electric Power System Coherent Sampling (ti.com). It uses the ADS131E, whereas we currently have the M, the only difference I can see between them is the maximum sampling frequency. Is it fair to say that this approach is suitable for the ADS131M04 as well?

    Many thanks,

    D M

  • 0 in reply to D M
    TI__Mastermind 35241 points

    Hi D M,

    Cole is out of the office right now, I can help support you while he is gone.

    That application note is a good place to start with respect to implementing coherent sampling in the ADS131M04. As you can probably tell from the app note, this is not a trivial task.

    It should also be noted that because the ADS131M04 is a delta-sigma ADC, the first few ADC data values immediately after fCLKIN changes are a mixture of data from the old modulator sampling rate and the new modulator sampling rate. For example, even if the CLKIN frequency change happens right after ADC data is finished, for SINC3, the next output ADC data will rely on 2*OSR number of old frequency modulator data and 1*OSR new frequency modulator data (roughly) and so on until the 3rd output data is 100% new frequency modulator data. This is true for any oversampling ADC with an integrated digital filter

    However, the error associated with this issue is likely better than the error inherent in noncoherent sampling

    -Bryan