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ADS131M03: About clock input spec

Luke Sakamoto
Intellectual 1345 points
Part Number: ADS131M03

Hi team,

My customer is asking about the clock input of this IC. Can you look at the below questions?

1. In low power mode, the IC should accept 0.3MHz～2.08MHz. Would there be any performance deference depending on the frequency in here?

2. Any paticular reason for "2.048Mhz" in the typ value of very-low-power mode? 

Thanks,

Luke

  • +1
    TI__Mastermind 35600 points

    Hi Luke,

    Please see the answers below:

    1. If the clock difference or issue (e.g. jitter) is not considered. In terms of ADC noise, there is no difference to use a different master clock frequency in theory when the OSR (oversampling ratio) setting for the internal digital filter is same. Changing the clock frequency will affect the modulator frequency that is half of the master clock, the bandwidth of the digital filter is related to the modulator frequency, so it is possible that the noise will change a bit because of the bandwidth change of the digital filter.
    2. The output data rate depends on the OSR and the modulator frequency that is half of the master clock. In order to get an integer data rate, the modulator frequency/master clock should be the integer multiple of the OSR, so 2.048Mhz/4.096Mhz/8.192Mhz are common clock frequencies used for delta-sigma ADCs. Also, the lower clock frequency, the lower power consumption, so 2.048Mhz clock frequency is used for VLP(very low-power) mode.

    Regards,

    Dale