Hello,
My customer has a question about the Power Trimming setting of the LM98640QML-SP.
Q1) How should the user enter values into the register map when trying to set to the case marked below?
Q2) Could you please explain the principle of how PGA and ADC power trimming operate in the device depending on the setting value?
Thank you.
JH
Hi JH,
For your highlighted setting,
PGA power trimming = 0x09, ADC power trimming = 0x00.
So,
PGA stage 2 bias current trimming = b001
PGA stage 1 bias current trimming = b001
All other bits in this register are 0
ADC current trimming 1 = b000
ADC current trimming 2 = b000
All other bits in this register are 0
Based on the operating frequency and PGA gain, these trim bits are programmed to set the optimum biasing for the internal PGA and ADC circuits for best performance.
Thanks,
Karthik
Hi Karthik,
Thanks for your reply.
The customer has further question about the ADC power trimming.
ADC power trimming sets up two stages of ADC current trimming as shown below.
Does the actual ADC current change through this setting?
For example, if set to 0x08, Stage2: 001, Stage1: 000, Stage2 is 50% Power, and Stage1 is 25% Power. Does this mean it will consume (50% + 25%)/2 = 37.5% Power?
Regards,
JH
Hi JH,
No, that is not correct understanding.
The intent of the ADC power trimming register is to set the right bias voltages and bias currents of internal circuits based on the sampling speed. Only the bias currents will change in steps of 25%. There will be some change in power, but not by 25% as shown in Table 6.
When the recommended settings are applied, the customer will show below supply currents for any given setting.
Thanks,
Karthik N
