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Original question:

LM98640 Digital I/O Voltage

LM98640QML-SP: LM98640

Scott Thomas
Prodigy 80 points
Part Number: LM98640QML-SP

TI_Genius Kirby stated that:

"The LVDS output runs off of the 1.8V drive.  The rest of the part runs off of the 3.3V supply.  The Vih and Voh are for the SPI and not for the LVDS output.  Please see the LVDS Output table for the LVDS specification."

Kirby states that the Vih and Voh levels are for the SPI.  The problem is that the Vih levels listed for SPI in table 6.6 correspond to a 3.3V interface but the Voh levels listed for SPI in table 6.6 correspond to 1.8V levels.  So is it not correct for Kirby to state that the rest of the part runs off of the 3.3V supply?

I am asking if the SPI interface is 1.8V or 3.3V.  The SPI input signals are listed with 3.3V levels but the SPI output signal is listed with a 1.8V level.

Note that Vih is for the SPI input signals SCLK, SEN, SDI and CLPIN, and that Voh is for the SPI output signal SDO.

Can Kirby or someone else please clarify?

Are the SPI input interfaces 3.3V signaling and the SPI output interfaces 1.8V signaling?  It is fine if it is but please clarify that it is that way.  It would just be nice if the datasheet stated that clearly.

Thank you,

scott

  • 0
    TI__Expert 4550 points

    Hi Scott, 

    I suppose you are referring to Kriby's response here. It is correct. Use 3.3V or 2.5V digital signaling for the SPI interface. 

    I disagree a bit with your analysis of the Voh levels. The minimum of Voh across all supply, temperature, process variation is given as 1.8V and typical is 1.93V. This is not possible with a 1.8V supply. But I do agree that the datasheet could have been clearer. Thanks for your feedback. 

    I also checked the LM98640EVM schematic here and the corresponding FPGA capture card (Wave vision 5) here. I see that a 2.5V I/O bank has been used on the FPGA for the SPI I/O signals. Can you follow the same? 

    Thanks, 

    Karthik 

  • 0
    Prodigy 80 points

    Hi Karthik,

    Thank you for your quick response.  I understand what you are saying.  I have a 3.3V I/O bank available for the SPI interface.  I will use 3.3V signaling if that is acceptable. 

    They do not list the SPI signals clearly in the absolute maximum ratings table.  Is the intent to say that "VDD33 pins" include pins that are powered with VDD33?  Is it correct to say that the SPI interface signals have absolute max levels of -0.3min and VDD33 +0.3 max, not to exceed 4.2V?

    Thank you for your support,

    Scott   

  • 0 in reply to Scott Thomas
    Prodigy 80 points

    Hi Karthik,

    Thank you for your quick response.  I understand what you are saying.  I have a 3.3V I/O bank available for the SPI interface.  I will use 3.3V signaling if that is acceptable. 

    They do not list the SPI signals clearly in the absolute maximum ratings table.  Is the intent to say that "VDD33 pins" include pins that are powered with VDD33?  Is it correct to say that the SPI interface signals have absolute max levels of -0.3min and VDD33 +0.3 max, not to exceed 4.2V?

    Thank you for your support,

    Scott   

  • 0 in reply to Scott Thomas
    Prodigy 80 points

    Hi Karthik,

    Also, can you please tell me if the SPI signals have diode protection similar to the "analog signals"?  Note 1 in section 6.6 shows diode protection connected to VA and AGND for "analog signals".  Is VA the same as VDD33 and is AGND the same as VSS33?  Do the SPI signals have this same protection?  Do all signals have this protection?

    Thank you for your support,

    Scott

  • 0 in reply to Scott Thomas
    TI__Expert 4550 points

    Hi Scott, 

    For your FPGA 3.3V I/O bank output lines (SCLK, SEN, SDI, CLPIN), can you ensure that VOH>2V, and VOL<0.8V? And for the input line (SDO), can you ensure that VIH<1.8V, and VIL>0.2V. Then, I don't see any problem with the interface. 

    "Is the intent to say that "VDD33 pins" include pins that are powered with VDD33? Is it correct to say that the SPI interface signals have absolute max levels of -0.3min and VDD33 +0.3 max, not to exceed 4.2V?" - Yes, this is correct.

    Yes, the SPI lines have diode protection as shown in Note 1 of Section 6.6 of the datasheet.

    Thanks,
    Karthik

  • 0 in reply to Karthik Nagabhushana
    Prodigy 80 points

    Hi Karthik,

    Since the SDO signal is driven by 3.3V logic would you agree that the FPGA input selected should have an absolute maximum voltage specification of greater than 3.3V?

    Thank you for your support,

    Scott  

  • 0 in reply to Scott Thomas
    TI__Expert 4550 points

    Hi Scott, 

    Yes, that is fair (3.3V or greater). 

    Thanks, 

    Karthik