ADS42JB49: Jump in voltage data

Hi Sharon,

I am looking into this. Would you be able to send us the full schematic and provide more details about your test setup?

One question comes to mind, are you using an amplifier to drive the ADC?

Also, I have a few questions on the SPI writes:

1. Are you using channel B? Register 0x8 is configured to power down channel A.

2. The User Guide configuration sets 19 frames per multiframe and you are programming 18 frames per multiframe. Is there a specific reason for choosing this value?

Best regards,

Drew

Hi Sharon,

Could you also please specify your sample rate?

Best regards,

Drew

Hi Drew,

Sample rate is 200MSPS. 

Unfortunately, I cannot share the full schematic. If you have questions about specific parts of the schematic or if there is a more private way for me to send you the schematic, I am happy to share more.

We had a front end amplifier but something about the connection between the two were causing oscillations so now we are directly injecting a signal that is within the input voltage limits into the ADC directly. 

We are using channel B, not A. I am using 19 frames per multiframe but the configuration parameters for K must be the binary value - 1 so that is why it is represented as 18. In the FPGA, I set K to be 19 and I see in the ILAS section that setting the ADC K to be 18 allows the two settings to match up and be verified by the FPGA.

Thank you Sharon for the details,

We would still like to know more about your test setup. What are you using to supply your signal? Is it a pulse generator? What is the part number?

I will send you an email about obtaining schematic information.

Best regards,

Drew