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ADS7886: ADC samples calculation and filter calculation

Prathmesh Kulkarni
Prodigy 160 points
Part Number: ADS7886

Hi,

1. I was looking for detailed calculations for 1MSPS for Fsclk of 20MHz.
The value which I get is 1.25MSPS but mentioned in the datasheet is 1MSPS for 20MHz.
Can you please help me what i am missing and what calculation is involved?

2. How to calculate the filter circuit for Vkick, Vsettle?

Thank you,

Thank You.

  • 0
    TI__Guru**** 168895 points

    Hi Prathmesh,

    The ADS7886 takes 16 clock cycles to do the conversion, so 800 nS at 20MHz.  It also needs 325 nS of acquisition time, but this actually starts before the conversion cycle is complete (see Figure 1, point b).  When you put the numbers for tq and td1 together, you get the 1 uS or 1 MSPS throughput timing.

    For Q2, you can use the Analog Engineers Calculator tool for that:

  • 0 in reply to Tom Hendrick
    Prodigy 160 points

    Hi,

    Thank you.

    But it's not matching

    800ns+tq(40ns)+td1(25ns)

    If its okay can you elaborate more?

    Or for 5MHz can you share calculation? 

  • 0 in reply to Prathmesh Kulkarni
    TI__Guru**** 168895 points

    OK - lets try this:

    Values in RED above are for the 20MHz clock.  For a 5MHz SCLK, you would have 3.2 uS (16 * 1/5MHz) in place of the 800nS.  The acquisition phase for sample N+1 would start 2.7uS into the conversion cycle (in place of the 675nS).  The minimum acquisition technically won't change, but due to the clocking out of the LSB's you are in the acquisition phase longer.  You still need the minimum tw1 time on the CS line. So, your throughput would be the 16 sclks plus the tw1 minimum.  

  • 0 in reply to Tom Hendrick
    Prodigy 160 points

    Hi Tom,

    Thank you for explanation.

    If its okay can you provide the 675ns(1usec) or 2.7ms calculation. 

    My apologies, I am not able to figure it out still trying to understand.

    Thank you.

  • 0 in reply to Prathmesh Kulkarni
    TI__Guru**** 168895 points

    Hi Prathmesh,

    For SAR converters like the ADS7886, there is a conversion phase and an acquisition phase.  In general, throughput is equal to the time it take to 1) acquire data and 2) convert the acquired sample.  The ADS7886 begins the acquisition cycle after 13.5 SCLKS.  At 20MHZ, the clock period is 50nS.  13.5 SCLK cycles times 50nS is 675nS, acquisition time is 325nS, so that is 1uS in total.  At 5MHz, you still have 13.5 SCLK cycles to get to the point where the next acquisition phase starts - so 13.5 * 200nS is the 2.7uS comes from.