Dear TI Teams,
When using the AFE5832LP in one of our projects, we encountered some problems with LVDS data reception, the details are as follows:
We know that the default of AFE5832LP is to transmit data of two AD acquisition channels on one LVDS line, and a total of 16 LVDS lines are used to transmit 32 channel datas, and the high FCLK is fixed to correspond to the even number of channels, and the low FCLK corresponds to the odd number of channels. At present, due to the limitation of system IO, we are using one LVDS line to transmit data from 4 AD acquisition channels, and a total of 8 lines are used to complete the acquisition and transmission (LVDS RATE 2X mode). In this case, the 4 channels acquired data at once are transmitted on a single LVDS line., corresponding to an acquisition of FCLK has two high level cycles and two low level cycles, will represented in high, low, high, low form, corresponding to the AD acquisition channel of 1st-ch, 3rd-ch, 2nd-ch, 4th-ch. Therefore, when FCLK is in high level, we can not determine whether the current corresponding to the data of channel 1 or channel 3 data.
From the datasheet we learned that after a certain delay time after TX_TRIG, the FCLK signal will regularly appear in high, low, high, low pulse signals, and then the first high signal corresponds to the data of the first channel. However, we found that the delay time is not fixed after each TX_TRIG generation, which will cause the confusion of solving the data channel. That is, the external input is fixed at 1 channel input, but after solving the data, sometimes the waveforms appear in the frist channel and sometimes in second channels.
May I ask if there is some mechanism to know exactly this correspondence?
Thanks,
Kind Regards
