Hi Folks,
The ADS8166’s SPI interface can operate @ 70MHz. The period of the clock cycle @ 70 MHz (~14.3 ns) is shorter than the 19ns (max) for the SDO delay (td_CKDO) from rising clock edge. So the delay could be 1-whole clock-cycle behind the SCLK.
Is there a discrepancy in the datasheet in this spec? Or is there some relation to the td_CKDO and SCLK frequency that prevents a potential misalignment of SDO information?
Thanks,