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AMC1035-Q1: edge selection for latching the modulator bitstream

Christian Sch.
Prodigy 60 points
Part Number: AMC1035-Q1
Other Parts Discussed in Thread: AMC1035, ISO7740, DS90LV027A, DS90LV028A, AMC1210, AMC1336

Hello,

in the datasheet of AMC1035 is written: "The modulator bitstream on the DOUT pin changes with the rising edge of the clock signal applied on the CLKIN pin. Use the rising edge of the clock to latch the modulator bitstream at the input of the digital filter device."
Why is it recommended to use the rising edge for latching the input data? The AMC1035 defines a minimum hold time tH1 of 6 ns and a maximum setup time tD1 of 25 ns (no manchester coding). If no other mismatch is inserted, the I would expect to use falling edge to read in the data, but the maximum setup time is very long with half period of 20 MHz, which would ideally be the falling edge moment.

For an isolated measurement I'm planning the following setup:

The ISO7740 is defined with a Channel-to-channel output skew time for Same-direction channels of maximum 4.1 ns.

The DS90LV027A is defined with a Channel to Channel Skew of maximum 0.8 ns.

The DS90LV028A is defined with a Differential Channel-to-Channel Skew-same device of maximum 0.5 ns

Therefore in sum a resulting timing mismatch between clock and data can be up to +/- 5.4 ns.

The AMC1210 requires a setup time before the rising edge of minimum 5 ns and a hold time after rising edge of minimum 5 ns.

If the minimum hold time of the AMC1035 was at least 5.4 ns + 5 ns = 10.4 ns, the the AMC1210 could work on rising edge.

If the maximum setup time of the AMC1035 was less than 25 ns - 5.4 ns - 5 ns = 14.6 ns, then the AMC1210 could work on falling edge.

So again the question: Can the AMC1035 setup time really be up to 25 ns? It seems to be such a large value.

Thanks,

Chris

  • 0
    TI__Expert 4125 points

    Hi Chris,

    Yes, the maximum delay from rising edge of CLKIN to DOUT is 25ns. I think this should be fine. 

    If the datasheet defines using the rising edge of the clock to latch the modulator bitstream at the input, then these are the directions needed for proper functionality. 

    Are you using the same clock for all of your devices?

    Best regards,

    Eva

  • 0 in reply to Eva Mason
    Prodigy 60 points

    Hi Eva,

    thank you for your quick answer. Yes, as you can see in my picture, the complete data acquisition path is driven by one single clock source.

    The receiving device AMC1210 uses the rising clock for latching the data, as suggested in the datasheet of the modulator. And the receiving device has a tight margin around the rising clock of only +/- 5 ns, defined by its minimum setup and hold time. But because the AMC1035 has just a minimum hold time of 6 ns, there is only 1 ns left for mismatch between data and clock. This prohibits to do any signal converting, because it is nearly impossible doing so, to keep the mismatch below 1 ns.

    Is the statement "Use the rising edge of the clock to latch the modulator bitstream at the input of the digital filter device." perhaps made by assuming, that the source of the clock signal is allocated to the receiving device, so that it already takes a time until the rising clock edge reached the AMC1035?

    Thanks and regards

    Christian

  • 0 in reply to Christian Sch.
    TI__Expert 4125 points

    Hi Christian,

    I see your timing concern. Unfortunately, the rising edge latch of the clock is not a specification we can modify. 

    Have you considered using the AMC1336 instead of the AMC1035+ISO7740? It has the same +/-1V input voltage range and integrated isolation. 

    Additionally, I think this Application Note could be helpful for your system. It includes a link to a timing calculator as well. 

    Best regards,

    Eva