DAC81408: Data converters forum

T.C

Part Number: DAC81408

Dear TI team

I have three questions for this DAC IC.

1. Is it correct that the power down mode function works at the timing of [power off → power on], and the glitch is 0.3V at the maximum?
Or is there a difference between power down mode and power off?

2. What is the voltage level the glitch of power on → power off?

3. Is there no sequence rule for power off as well?
Also, what is the recommended sequence to reduce the glitch?

Best regards,

T.C.

3 months ago

0 Katlynne Jones 3 months ago

TI__Mastermind 28828 points

Hi T.C.,

Sanjay will review your questions and provide a response soon.

Best,

Katlynne Jones

0 Sanjay 3 months ago in reply to Katlynne Jones

TI__Intellectual 2370 points

Hi T.C.,

Please check my response below for each line item -

1. Is it correct that the power down mode function works at the timing of [power off → power on], and the glitch is 0.3V at the maximum?
Or is there a difference between power down mode and power off?

- Yes, the power down mode function works at the timing of [power off → power on], and the glitch is 0.3V at the maximum. This is to check the DAC output enable glitch magnitude.

2. What is the voltage level the glitch of power on → power off?

- Currently there is no such data sheet specification available for power on → power off but it should not be much different from the power off → power on glitch magnitude.

3. Is there no sequence rule for power off as well?
Also, what is the recommended sequence to reduce the glitch?

- Yes, there is no sequence rule for power off. Recommended sequence to reduce the glitch is first power on VAA/VDD/VIO and then VCC/VSS, REFIO should come up at the end.

Thanks,

Sanjay