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ADC128S052-Q1: Degradation when running SCLK lower than 3.2 MHz

Part Number: ADC128S052-Q1

Hi,

Can TI provide more details about the degradation described at

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1278700/adc128s052-q1-sclk-frequency

when the ADC128S052-Q1 SCLK is less than 3.2 MHz? We are specifically looking at running SCLK between 500 kHz to 2 MHz and need to understand all the possible degradations in the device operations.

Thank you!

Brian

  • Hi Brian,

    Thanks for your question. As this is an older National Semiconductor device, unfortunately we do not have test data at those lower clock speeds. As far as I'm aware, going below 3.2MHz may degrade the AC performance by ~1dB, nothing drastic. I wouldn't recommend going below the 800kHz minimum clock speeds though, as I am uncertain how the performance would change at that point.

    Best regards,

    Samiha