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Hi Experts,
Good day.
Paragraph 7.4.2.1. RESET state
"In order to exit any of the RESET states, the RST pin must be pulled high with CONVST/CS and SCLK held low.
After a delay of tD_RST_POR or tD_RST_APP (see the Timing Requirements: Asynchronous Reset table), the device
enters ACQ state and the RVS pin goes high"
Does this mean that CONVST/CS and SCLK must be held low during the RST low-high transition, or does the ADS8689 leave the RESET state the at the earliest occasion when /RST high, /CS low and SCLK low applies concurrently?
Thank you for your assistance.
Regards,
Archie A.
Hi Archie,
The top of the 7.4.2.1 section tells you that it is an asynchronous reset, so getting into the reset state is easy. Once you release /RST, you can re-configure the part. SCLK is low by default so if you want to resume conversions, SCLK should be low with CONVST high.