TSW14J58EVM: Recommended FPGA Sample Design for ADC32RF55EVM

Shunya Matsushima

Part Number: TSW14J58EVM
Other Parts Discussed in Thread: ADC32RF55, TI-JESD204-IP

Tool/software:

I am conducting operation verification and learning with the above evaluation board, aiming at FPGA development to communicate with ADC32RF55.

I was able to verify the operation according to the user guide, but I am looking for parameters related to the internal FPGA implementation and JESD204B for learning.

sbau377.pdf (ti.com)

・Please let me know if any information about the FPGA for TSW14J58 written by HSDC Pro is available.

　The information I am particularly interested in includes the K parameter and information about the delay of SYSREF.

　If that is not available, please tell me the closest design. The important settings are LMFS=8224 / GTY / 14bit.

・Is it enough to prepare for writing to this evaluation board with JTAG by simply changing J29 to 2 to 3 > 1 to 2?

・Separately, sometimes the current value does not stabilize when operating as per the above product guide. Please let me know if there is a way to improve this.

over 1 year ago

+1 Chase W over 1 year ago

TI__Mastermind 23720 points

Hi Shunya,

These details I can try to answer. The K value can be found by accessing the FPGA Registers Write/Read menu option. Scroll down to Dataconverter IP and click on Link Parameter Control. The K value is bits 24:16 of this field.

JTAG can be used without any jumper position changes if using the 14 pin header for JTAG.

The FPGA firmware for the evaluation board was created by third party contractor prior to creation of our TI-JESD204-IP. https://www.ti.com/tool/TI-JESD204-

We cannot provide the source code for the firmware used by the evaluation platform. If interested in example code, you must complete the IP request shown above and a reference design will be created and provided to you for your specific mode.

Thanks, Chase

0 Shunya Matsushima over 1 year ago in reply to Chase W

Prodigy 70 points

Thank you so much! I was able to check the parameter value.

It was very helpful!

On the other hand, the phenomenon of the current value not stabilizing occurs irregularly. Is this impossible to improve?

0 Chase W over 1 year ago in reply to Shunya Matsushima

TI__Mastermind 23720 points

Hi Shunya,

I am not sure what you are referring to by the "current value" not stabilizing.

Thanks, Chase

0 Shunya Matsushima over 1 year ago in reply to Chase W

Prodigy 70 points

The "current value" refers to the current value being inputted into the TSW14J58.

In the User Guide, it is written that it stabilizes at 2.1 A, but there are times when it can drop close to 0 A.

This frequently happens in both the JTAG writing operation and the Quick Start Procedure.

> sbau377.pdf (ti.com) 6 Page

+1 Chase W over 1 year ago in reply to Shunya Matsushima

TI__Mastermind 23720 points

During programming it can drop as low as 500mA. This is normal.

0 Shunya Matsushima over 1 year ago in reply to Chase W

Prodigy 70 points

We are aware that the current value changes during the writing process.

The current value drops to about 0.2A when it decreases. This can suddenly occur immediately after startup or during operation after writing.

In this case, the LED turns off, and the written data in the FPGA is lost.

If there are no similar reports with this EVM board, it might be an issue with the stabilization power supply.

0 Chase W over 1 year ago in reply to Shunya Matsushima

TI__Mastermind 23720 points

Hi Shunya,

If the board is operational after programming, I would not suspect the hardware to be at fault. I'm not sure how the supplies respond to jtag for programming the fpga but it may have something to do with it

Thanks, Chase

0 Shunya Matsushima over 1 year ago in reply to Chase W

Prodigy 70 points

Thank you for your response.

If there is no issue with the hardware, we will review the program.

Thank you for your answer! Please close this.

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TSW14J58EVM: Recommended FPGA Sample Design for ADC32RF55EVM