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ADS1278: SPI TIMING ISSUE

AJITH KUMAR
Intellectual 490 points
Part Number: ADS1278

Tool/software:

Hi Support Team,

In ADS1278 datasheet the timing sequence is,

But we are occuring, when DRDY falling low. In 60ns SCLK should transfer the clock. But it took times upto 532ns. we need to reduce this timing.

And DRDY pin falling edge to next falling edge timing is 15 us but it was 17 us sec . 

We need to reduce the timing.

Kindly do needful.

Thanks and Regards,

A. Ajith Kumar

  • 0
    TI__Mastermind 46231 points

    Hi AJITH KUMAR,

    One of your colleagues appears to be asking the same or similar questions. The thread title is the same

    Can you please coordinate with each other and make sure the question is only being asked once. It is not a good use of our time to have to respond to the same question multiple times.

    https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1377406/ads1278-spi-timing-issue

    -Bryan

  • 0 in reply to Bryan Lizon86
    Intellectual 490 points

    Hi Bryan,

    The question is different from this thread but the topic is same for both.

    Kindly do needful.

    Thanks and Regards,

    A. Ajith Kumar

  • 0 in reply to AJITH KUMAR
    TI__Mastermind 43140 points

    Hello Ajith,

    The data rate, or period of /DRDY, is determined by the ADC clock frequency, and the pin configurations for speed and clock division.

    Please provide the clock frequency used as well as the speed mode and CLKDIV settings.

    Also, the timing from /DRDY falling to the first SCLK is entirely determined by your system processor and code, and is not related to any timing on the ADS1278.  As such, you will need to look at your code and processor datasheet to determine how to reduce this timing.  The first SCLK edge can be as short as 1 t-CLK period after /DRDY falling edge.  Assuming you are using a 27MHz main clock for the ADS1278, the minimum delay would then be 38ns.

    Regards,
    Keith Nicholas
    Precision ADC Applications