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DAC5687-EP: DAC5687 SPI Communication Error

Mustafa Dursun
Prodigy 90 points
Part Number: DAC5687-EP
Other Parts Discussed in Thread: DAC5687

Tool/software:

Hi,

I am trying to change register values of DAC5687 through SPI over 4-wire on our custom board. First write operation is to open 4-wire mode. However when I read back the data, it is always zero. 

Actually, MISO pin is always zero volt whether SDENB active or not. 

What can be the reason of this behaviour?

Best Regards,

Mustafa

  • 0
    TI__Mastermind 20155 points

    Hi Mustafa,

    I would check that the bootstrap pin RESETB is not held low for any reason. I’m not an expert on this device but in the past when I’ve had spi related issues and have measured on a scope that the SPI clock and data is at the device pins at the appropriate levels, that the issue is typically the device is being held in reset. Do you have any voltage supervisor circuitry on this custom board that isn’t satisfying which may be causing this?

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 90 points

    Hi Chase,

    There is not any voltage supervisor circuitry on the board. There are only LDO's which are enabled on hardware. I was holding RESETB pin at logic-0 for 500ms from processor side.. With your suggestion I have comment out this step. Now, I am driving it logic-1 always and also there is a pull-up on RESETB signal on the board. 

    As you mentioned, I have also checked the SCLK, SDIO and SDENB signals with an osiloscpoe it seems that their voltage levels and transitions are appropriate. And also SDIO transitions occur at falling edge of SCLK.

    However the problem still exists.

    Does power-up sequencing effect the SPI interface behaviour? It is stated in the datasheet that "In all conditions, bring up DVDD first". Is there a duration limit to enable other voltages after DVDD up? 

    Currently all of the supplies start to ramp up together on the board.

    Also note that other pins are being driven as following:

    PHSTR: Logic-1

    QFLAG: Logic-0

    TXENABLE: Logic-0 at the startup and Logic-1 after SPI transactions.

    SLEEP: Logic-0

    CLK1 and CLK2: There are differential 125MHz clock at both clock inputs. Vpp is approximately 1V. I have measured common mode voltages(VCM) of CLK2 inputs are 1.6V BUT VCMs of CLK1 inputs are 0V. Is it normal or may be, is it the reason of SPI communication problem?

    Best Regards,

    Mustafa