This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1299-4: Clock signal requirements

Part Number: ADS1299-4
Other Parts Discussed in Thread: ADS1299

Tool/software:

Dear all,

I would like to divide an existing 24.576MHz clock by 12 to drive the 2.048MHz clock input of the 1299.

My question:

Must this 2.048MHz clock be square, i.e. 50% duty, or would a 33% duty cycle suffice?

In other words: can I use bit 3 of a 4 bit counter that resets after count 11?

Best regards,

Andre

  • Hi Andre,

    Thank you for your post.

    There is no strict duty cycle requirement for the ADS1299. The modulator clock which controls the ADC sample timing is derived by dividing the master clock input by a factor of 4.

    That being said, I also do not believe this has been tested. Do you see a benefit to generating your clock this way as opposed to using the device's internal oscillator?

    Regards,

    Ryan

  • Dear Ryan,

    thanks a lot for the quick reply!

    Actually, we want to sync the chip to an audio stimulus, generated by a codec that derives its 48kHz sampling rate from a 24.576MHz clock. The easiest way of doing so would be to divide that clock by 12.

    To play it safe, however, we will spend one more flipflop to create a square 2.048MHz.

    Best regards,

    Andre