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Tool/software:
In my project, I am using the ADC3444, and we are planning to use the AXI Quad SPI controller for control purpose it's from Xilinx. The AXI Quad SPI controller in standard mode supports 8, 16, or 32-bit data frames. However, the ADC3444 datasheet mentions that serial data is loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data may be loaded in multiples of 24-bit words within a single active SEN pulse.
Given that the ADC3444 supports only 24-bit data frames and the AXI Quad SPI controller does not support 24-bit frames, is there any alternative solution for interfacing the ADC3444 with the AXI Quad SPI controller? If not, what other methods or controllers would you recommend for this purpose?
Hi Keerthana,
We use USB connection for SPI on our evaluation hardware(s). This post from AMD seems helpful. https://adaptivesupport.amd.com/s/question/0D52E00006hpi5HSAQ/using-axi-quad-spi-to-connect-to-classic-adc-interface?language=en_US
There doesn't look to be a way to natively support it without writing your own wrapper around it at least and breaking into 3x8-bit transactions instead. Just ensure the code allows for the SEN pin to be low throughout the full transactions.
Thanks
Thanks chase for your reply,
if we write RTL for the SPI Controller , is it better than using the 3x8 bit transaction in the AXI QUAD SPI controller?
Hi Keerthana, I work on the ADC side and not on the FPGA side so I am not able to give a definitive answer. I would lean towards saying discrete RTL that is specific for handling common 24-bit transactions will be better than stitching together the smaller transactions but it is up to you to decide effort level etc. We cannot provide support on this topic so for any further discussion your best option is to go to amd/xilinx for support.
Thanks