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ADS1292R: Insufficient sampling rate

Yingying Zheng
Prodigy 20 points
Part Number: ADS1292R
Other Parts Discussed in Thread: ADS1292

Tool/software:

Hello, TI engineers! I only used one ADS1292R to test one channel of ECG and one channel of respiration.  I have a question about the sampling rate of ADS1292R. When I set the sample rate to 500Hz, the actual sampled and recorded data is not that much, and the fluctuation is large. What is the reason for this situation?

Some of my output logs are as follows：

ECG sample rate: 206.0 Hz
ECG sample rate: 160.199 Hz
ECG sample rate: 247.75224 Hz
ECG sample rate: 139.58125 Hz
ECG sample rate: 130.86913 Hz
ECG sample rate: 108.0 Hz
ECG sample rate: 330.7241 Hz
ECG sample rate: 437.68692 Hz
ECG sample rate: 407.59238 Hz
ECG sample rate: 439.0 Hz
ECG sample rate: 448.0 Hz
ECG sample rate: 436.255 Hz
ECG sample rate: 393.76218 Hz
ECG sample rate: 451.0 Hz
ECG sample rate: 382.0 Hz
ECG sample rate: 466.53345 Hz
ECG sample rate: 429.5704 Hz
ECG sample rate: 417.0 Hz
ECG sample rate: 462.53745 Hz



  • 0
    TI__Guru 64046 points

    Hi Yingying,

    Thank you for your post.

    What are you basing the "ECG sample rate" on? If you probe the /DRDY output signal, you should see that the period between falling edges coincides with data rate, assuming you are in Continuous Conversion Mode. /DRDY is cleared high on the first SCLK falling edge, so the time between consecutive rising edges will be dependent on when your host controller reads the data. 

    Regards,

    Ryan

  • 0 in reply to Ryan Andrews
    Prodigy 20 points
    My register settings are as follows：
    ADS1292_REG_CONFIG1, 0x02
    ADS1292_REG_CONFIG2, 0b10100000
    ADS1292_REG_LOFF, 0b00010000
    ADS1292_REG_CH1SET, 0b01000000
    ADS1292_REG_CH2SET, 0b01100000
    ADS1292_REG_RLDSENS, 0b00101100
    ADS1292_REG_LOFFSENS, 0x00
    ADS1292_REG_RESP1, 0b11110010
    ADS1292_REG_RESP2, 0b00000011
    In the continuous conversion mode, the sampled data transmitted to the PC for 1s is calculated. The results show that it has not reached 500Hz stably for a period of time.Is there any other way I can check if the sampling rate meets the requirement? Can I only detect the /DRDY output signal to see if the period between the falling edges matches the data rate?
  • 0 in reply to Yingying Zheng
    TI__Guru 64046 points

    Yes, first I would check the ADS1292 device itself. You can also probe the SPI signals and confirm that each transaction begins and ends within one data rate period. This means that /CS should go low after the /DRDY falling edge, and all 72 bits (STATUS + CH1 + CH2) should be read before the next /DRDY interrupt.

    Regards,

    Ryan