TI-JESD204-IP: TI-JESD204-IP: Simulation in Vivado 2023.1

Daniel Urdaneta

Part Number: TI-JESD204-IP

Tool/software:

Hi,

I'm trying to simulate the reference design of the JESD204-IP and not getting any result. Every signal that comes out of the IP appears as a high-impedance signals.

I'm driving the master_reset to '1' first and then the tx/rx_sync_reset_vio to '0' after 200 ns. The JESD204-IP is configured as it comes, no changes are being made to the verilog header file or any other file.

I tried to run the simulation for the zcu102_8b10b as well as the vcu118_64b66b reference_designs in vivado 2023.1, same result with both.

Thanks,

Daniel Urdaneta

3 months ago

0 Ameet Bagwe 2 months ago

TI__Intellectual 2260 points

Hi Daniel,

Kindly confirm if you have connected the top level signals as specified in section 8.6.2 of the user guide. It seems like a number of signals are undriven. In addition, is the TI IP core included in the list of files?

Regards,
Ameet

0 Daniel Urdaneta 2 months ago in reply to Ameet Bagwe

Prodigy 10 points

Hi Ameet,

Yes, we are following the guidelines specified on the TI204C-IP JESD FPGA IP User Guide. Section 8.6 Testing the Reference Design. The picutre below show the resets signals.

Also, the IP CORE was added to the project, but i`m not sure if there are any files missing since the IP is shown as encrypted. To add the IP to the project i'm adding the files TI_204c_IP.svp and TI_204c_IP_entity.sv found on the RTL folder (JES204C_IP_SRC/TI204C-IP-Release-v1.12-LATEST/TI-204c-CoreIP/Vivado_2022_and_Newer/rtl)

0 Ameet Bagwe 2 months ago in reply to Daniel Urdaneta

TI__Intellectual 2260 points

Hi Daniel<

Please remove the *_entity.sv file. It is meant to be used only as a reference for instantiation (as the core file is encrypted).

Other than that, everything else should work in simulations if you haven't made any changes to the original reference design.

Regards,
Ameet

0 Daniel Urdaneta 2 months ago in reply to Ameet Bagwe

Prodigy 10 points

After removing the TI_204c_IP_entity.sv from the project and following the guidelines of this post https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1230925/ti-jesd204-ip-simulation-of-loopback-design-in-vivado , the simulation shows activity on the tx lane.

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TI-JESD204-IP: TI-JESD204-IP: Simulation in Vivado 2023.1